Datasheet

Rev.7.00 Feb. 14, 2007 page xix of xxxii
REJ09B0089-0700
6.6.2 Pin States in Idle Cycle ........................................................................................176
6.7 Bus Release.......................................................................................................................177
6.7.1 Overview..............................................................................................................177
6.7.2 Operation .............................................................................................................177
6.7.3 Pin States in External Bus Released State............................................................178
6.7.4 Transition Timing ................................................................................................179
6.7.5 Usage Note...........................................................................................................180
6.8 Bus Arbitration..................................................................................................................180
6.8.1 Overview..............................................................................................................180
6.8.2 Operation .............................................................................................................180
6.8.3 Bus Transfer Timing............................................................................................181
6.8.4 External Bus Release Usage Note........................................................................181
6.9 Resets and the Bus Controller...........................................................................................181
Section 7 Data Transfer Controller....................................................................183
7.1 Overview...........................................................................................................................183
7.1.1 Features................................................................................................................183
7.1.2 Block Diagram.....................................................................................................184
7.1.3 Register Configuration.........................................................................................185
7.2 Register Descriptions........................................................................................................186
7.2.1 DTC Mode Register A (MRA) ............................................................................186
7.2.2 DTC Mode Register B (MRB).............................................................................187
7.2.3 DTC Source Address Register (SAR)..................................................................189
7.2.4 DTC Destination Address Register (DAR)..........................................................189
7.2.5 DTC Transfer Count Register A (CRA) ..............................................................189
7.2.6 DTC Transfer Count Register B (CRB)...............................................................190
7.2.7 DTC Enable Registers (DTCER).........................................................................190
7.2.8 DTC Vector Register (DTVECR)........................................................................191
7.2.9 Module Stop Control Register (MSTPCR)..........................................................192
7.3 Operation...........................................................................................................................193
7.3.1 Overview..............................................................................................................193
7.3.2 Activation Sources...............................................................................................197
7.3.3 DTC Vector Table................................................................................................198
7.3.4 Location of Register Information in Address Space............................................201
7.3.5 Normal Mode.......................................................................................................202
7.3.6 Repeat Mode........................................................................................................203
7.3.7 Block Transfer Mode...........................................................................................204
7.3.8 Chain Transfer .....................................................................................................206
7.3.9 Operation Timing.................................................................................................207
7.3.10 Number of DTC Execution States .......................................................................208