Datasheet

Section 6 Bus Controller
Rev.7.00 Feb. 14, 2007 page 165 of 1108
REJ09B0089-0700
16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed, the upper half (D
15
to D
8
) of the data bus is used
for the even address, and the lower half (D
7
to D
0
) for the odd address.
Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D
15
to D
8
Valid
D
7
to D
0
Invalid
Read
HWR
LWR
D
15
to D
8
Valid
D
7
to D
0
High impedance
Write
High
Note: n = 0 to 7
T
3
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)