Datasheet

Section 6 Bus Controller
Rev.7.00 Feb. 14, 2007 page 148 of 1108
REJ09B0089-0700
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
W11
Bit 2
W10 Description
0 0 Program wait not inserted when external space area 1 is accessed
1 1 program wait state inserted when external space area 1 is accessed
1 0 2 program wait states inserted when external space area 1 is accessed
1 3 program wait states inserted when external space area 1 is accessed
(Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
Bit 0
W00 Description
0 0 Program wait not inserted when external space area 0 is accessed
1 1 program wait state inserted when external space area 0 is accessed
1 0 2 program wait states inserted when external space area 0 is accessed
1 3 program wait states inserted when external space area 0 is accessed
(Initial value)
6.2.4 Bus Control Register H (BCRH)
Bit : 7 6 5 4 3 2 1 0
ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — —
Initial value : 1 1 0 1 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.