Datasheet

Section 5 Interrupt Controller
Rev.7.00 Feb. 14, 2007 page 125 of 1108
REJ09B0089-0700
Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt
acceptance
control
8-level
mask control
Default priority
determination
Vector numbe
r
Interrupt control mode 2
IPR
Interrupt source
I2 to I0
Interrupt
control
mode 0 I
Figure 5.4 Block Diagram of Interrupt Control Operation
Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by
the I bit in CCR.
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits
Interrupt Control Mode I Selected Interrupts
0 0 All interrupts
1 NMI interrupts
2 * All interrupts
* : Don't care