Datasheet

Appendix C I/O Port Block Diagrams
Rev.7.00 Feb. 14, 2007 page 1093 of 1108
REJ09B0089-0700
R
PG2DDR
C
QD
Reset
WDDRG
Reset
WDRG
R
PG2DR
C
QD
PG2
RDRG
RPORG
Bus controller
Port
Chip select 2
Mode 7
Internal data bus
CS25E bit
Modes
4 to 6
Legend:
WDDRG: Write to PGDDR
WDRG: Write to PGDR
RDRG: Read PGDR
RPORG: Read port G
CS25E: CS25 enable
Figure C.11(c) Port G Block Diagram (Pin PG2)