Datasheet

Appendix C I/O Port Block Diagrams
Rev.7.00 Feb. 14, 2007 page 1072 of 1108
REJ09B0089-0700
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n
RDR1
RPOR1
Internal data bus
TPU module
Output compare output
/
PWM output enable
Output compare output
/
PWM output
External clock input
Input capture input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: n = 5 or 7
Figure C.1(d) Port 1 Block Diagram (Pins P15 and P17)