Datasheet

Appendix C I/O Port Block Diagrams
Rev.7.00 Feb. 14, 2007 page 1070 of 1108
REJ09B0089-0700
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
Modes 4 to 6
R
P1nDR
C
QD
P1n
RDR1
RPOR1
Internal data bus Internal address bus
Bus controller
TPU module
AmE bit
Output compare output
/
PWM output enable
Output compare output
/
PWM output
External clock input
Input capture input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
AmE: Address m enable
Notes: n = 2 or 3
m = 22 or 23
Figure C.1(b) Port 1 Block Diagram (Pins P12 and P13)