Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 1039 of 1108
REJ09B0089-0700
TCNT—Timer Counter H'FFBC (W), H'FFBD (R) WDT
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Note: The method for writing to TCNT different from that for general registers to prevent
accidental overwritting. For details, see section 11.2.4, Notes on Register Access.
RSTCSR—Reset Control/Status Register H'FFBE (W), H'FFBF (R) WDT
7
WOVF
0
R/(W)*
6
RSTE
0
R/W
5
⎯
0
R/W
4
⎯
1
⎯
3
⎯
1
⎯
0
⎯
1
⎯
2
⎯
1
⎯
1
⎯
1
⎯
0
1
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF.
Watchdog Timer Overflow Flag
Notes: The method for writing to RSTCSR is different from that for general registers to preven
t
accidental overwriting. For details, see section 11.2.4, Notes on Register Access.
* Can only be written with 0 for flag clearing.
0
1
Reset Enable
Reset signal is not generated if TCNT overflows*
Reset signal is generated if TCNT overflows
Reserved
This bit should be written with 0.
Bit
Initial value
Read/Write
:
:
:
[Setting condition]
When TCNT overflows (changes from H'FF to H'00) during
watchdog timer operation
Note: * The modules in the chip are not reset,
but TCNT and TCSR in WDT are reset.