Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 1031 of 1108
REJ09B0089-0700
ADCSR—A/D Control/Status Register H'FF98 A/D Converter
[Clearing conditions]
• When 0 is written to the ADF flag after reading ADF = 1
• When the DTC is activated by an ADI interrupt, and ADDR is read
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Note: * Can only be written with 0 for flag clearing.
0
1
A/D conversion end interrupt request disabled
A/D conversion end interrupt request enabled
A/D Interrupt Enable
0
1
Single mode
Scan mode
Scan Mode
Group
Selection
CH2 CH1 CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
Channel
Selection
Description
0
1
A/D conversion stopped
A/D Start
0
A/D End Flag
Bit
Initial value
Read/Write
:
:
:
• Single mode: A/D conversion is started. Cleared to 0 automatically when
conversion ends
• Scan mode: A/D conversion is started. Conversion continues sequentially
on the selected channels until ADST is cleared to 0 by software, a reset,
or transition to standby mode or module stop mode
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
1
0
1
0
1
0
1
Description
Clock Select
CKS is used in combination with CKS1, bit 3 in ADCR.
Conversion time = 530 states (max.)
Conversion time = 68 states (max.)
Conversion time = 266 states (max.)
Conversion time = 134 states (max.)
CKSCKS1
Bit 3
ADCR
Bit 3
Single Mode
(SCAN = 0)
Scan Mode
(SCAN = 1)
Channel Select
Note: These bits select the analog input channel(s).
Ensure that conversion is halted (ADST = 0) before making
a channel setting.