Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 995 of 1108
REJ09B0089-0700
DTVECR—DTC Vector Register H'FF37 DTC
7
SWDTE
0
R/W
6
DTVEC6
0
R/(W)
*
5
DTVEC5
0
R/(W)
*
4
DTVEC4
0
R/(W)
*
3
DTVEC3
0
R/(W)
*
0
DTVEC0
0
R/(W)
*
2
DTVEC2
0
R/(W)
*
1
DTVEC1
0
R/(W)
*
DTC Software Activation Enable
0
1
DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Sets vector number for DTC software activation
Bit
Initial value
Read/Write
:
:
:
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTC software activation is disabled
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have
not ended
• When 0 is written to the SWDTE bit after a software activated data
transfer end interrupt (SWDTEND) has been requested of the CPU