To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2319 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series Rev.7.00 2007.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Rev.7.00 Feb.
Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules.
• In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.3.1 Pin Arrangement 13 Figure 1.6 amended (Before) TLP-113V (Top View) → (After) (Top View) Figure 1.6 HD64F2319CLP, HD6432317SLP, HD6432316SLP Pin Arrangement (TLP113V: Top View) 45 2.6.3 Table of Instructions Classified by Function Table 2.3 amended MOVFPE, MOVTPE (Before) Cannot be used in the H8S/2357 Series. → (After) Cannot be used in the H8S/2319 Group. Table 2.3 Instructions Classified by Function 6.3.
Item Page Revision (See Manual for Details) 8.4.2 Register Configuration 247, 248 Port 3 Data Direction Register (P3DDR) Port 3 Data Register (P3DR) Port 3 Register (PORT3) Port 3 Open Drain Control Register (P3ODR) Description amended (Before) ... retains its prior state after in software standby mode. → (After) ... retains its prior state in software standby mode. 8.6.
Item Page Revision (See Manual for Details) 12.2.8 Bit Rate Register (BRR) 452 Table 12.3 amended φ = 25 MHz Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 14.4.3 Input Sampling and A/D Conversion Time 545 Bit Rate (bits/s) n N Error (%) 110 3 110 –0.02 150 3 80 300 2 162 –0.15 600 2 80 0.47 0.47 1200 1 162 –0.15 2400 1 80 0.47 4800 0 162 –0.15 9600 0 80 0.47 19200 0 40 –0.76 31250 0 24 0.00 38400 0 19 1.73 Figure 14.
Item Page Revision (See Manual for Details) 17.8.3 Error Protection 604 Description amended (Before) • When a bus master other than the CPU (the DMAC or DTC) has control ... → (After) • When a bus master other than the CPU (the DTC) has control ... 17.11.2 Socket 609 Adapters and Memory Map 17.13.1 Features 629 Description added In programmer mode, ... figure 17.21. This enables the chip to fit a 40-pin socket. Figure 17.20 shows ...
Item Page Revision (See Manual for Details) 17.24.2 User Program Mode 729 Programming Procedure in User Program Mode: Description amended (g) Initialization • 730 (l) Programming • 17.25 Protection 738 The general registers other than ER0 and ER1 are saved in the initialization program. The general registers other than ER0 and ER1 are saved in the programming program.
Item Page 17.29.1 Serial 773 Communication Interface Specification for Boot Mode Revision (See Manual for Details) Programming/Erasing State (4) 128-Byte Programming Description amended • ERROR: (1 byte) Error code H'11: Checksum error H'2A: Address error 17.29.3 Procedure 791 Program and storable Area for Programming Data Table 17.73 (3) Usable Area for Programming in User Boot Mode 19.1 Overview Table 17.
Item Page Revision (See Manual for Details) 20.2.6 Flash Memory Characteristics 848 "⎯Preliminary⎯" deleted from table 20.19 Table 20.19 Flash Memory Characteristics 817 20.1 Electrical Characteristics of Mask ROM Version (H8S/2319, H8S/2318, H8S/2317S, H8S/2316S, H8S/2315, H8S/2314) and ROMless Version (H8S/2312S) Section 20.1 title amended 20.2.6 Flash Memory 849 Characteristics Table 20.19 amended Item Table 20.
Item Page 20.3.6 Flash Memory 860 Characteristics Table 20.29 Flash Memory Characteristics Revision (See Manual for Details) Table 20.29 amended Item Symbol NWEC Min 100*3 Typ Number of overwrites Data retention time *4 Max 10000*5 — Times tDRP 10 — Years — Unit Test Conditions Note 5 added Note: 5. Reference value for 25°C (as a guideline, rewriting should normally function up to this value). Appendix E Products 1103 Lineup Table E.1 amended Table E.
Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 8 Pin Description..................................................................................................
2.8.5 Bus-Released State............................................................................................... 66 2.8.6 Power-Down State ............................................................................................... 66 2.9 Basic Timing ..................................................................................................................... 67 2.9.1 Overview..............................................................................................................
3.5 Memory Map in Each Operating Mode ............................................................................ 81 Section 4 Exception Handling ...........................................................................99 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Overview........................................................................................................................... 99 4.1.1 Exception Handling Types and Priority............................................................... 99 4.1.
5.5 5.6 Usage Notes ...................................................................................................................... 134 5.5.1 Contention between Interrupt Generation and Disabling..................................... 134 5.5.2 Instructions that Disable Interrupts ...................................................................... 135 5.5.3 Times when Interrupts are Disabled .................................................................... 135 5.5.
6.7 6.8 6.9 6.6.2 Pin States in Idle Cycle ........................................................................................ 176 Bus Release....................................................................................................................... 177 6.7.1 Overview.............................................................................................................. 177 6.7.2 Operation .............................................................................................
7.4 7.5 7.3.11 Procedures for Using DTC................................................................................... 210 7.3.12 Examples of Use of the DTC ............................................................................... 211 Interrupts ........................................................................................................................... 215 Usage Notes ...................................................................................................................
8.9.2 Register Configuration......................................................................................... 272 8.9.3 Pin Functions ....................................................................................................... 275 8.9.4 MOS Input Pull-Up Function............................................................................... 276 8.10 Port E ................................................................................................................................
9.5 9.6 9.7 9.4.3 Synchronous Operation........................................................................................ 349 9.4.4 Buffer Operation .................................................................................................. 351 9.4.5 Cascaded Operation ............................................................................................. 355 9.4.6 PWM Modes ........................................................................................................ 357 9.
10.6.3 10.6.4 10.6.5 10.6.6 Contention between TCOR Write and Compare Match ...................................... 410 Contention between Compare Matches A and B ................................................. 411 Switching of Internal Clocks and TCNT Operation............................................. 411 Interrupts and Module Stop Mode ....................................................................... 413 Section 11 Watchdog Timer ...............................................................
12.2.5 Serial Mode Register (SMR)................................................................................ 438 12.2.6 Serial Control Register (SCR).............................................................................. 441 12.2.7 Serial Status Register (SSR) ................................................................................ 445 12.2.8 Bit Rate Register (BRR) ...................................................................................... 449 12.2.
14.2 14.3 14.4 14.5 14.6 14.1.3 Pin Configuration................................................................................................. 533 14.1.4 Register Configuration......................................................................................... 534 Register Descriptions ........................................................................................................ 535 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 535 14.
17.1.2 Register Configuration......................................................................................... 566 17.2 Register Descriptions ........................................................................................................ 566 17.2.1 Mode Control Register (MDCR) ......................................................................... 566 17.2.2 Bus Control Register L (BCRL) .......................................................................... 567 17.3 Operation.........
17.12 17.13 17.14 17.15 17.16 17.11.1 Progremmer Mode Setting ................................................................................... 608 17.11.2 Socket Adapters and Memory Map...................................................................... 609 17.11.3 Programmer Mode Operation .............................................................................. 611 17.11.4 Memory Read Mode ............................................................................................ 613 17.11.
17.17 Flash Memory Protection.................................................................................................. 662 17.17.1 Hardware Protection ............................................................................................ 662 17.17.2 Software Protection.............................................................................................. 663 17.17.3 Error Protection....................................................................................................
17.26 17.27 17.28 17.29 17.25.1 Hardware Protection ............................................................................................ 738 17.25.2 Software Protection.............................................................................................. 739 17.25.3 Error Protection.................................................................................................... 739 Flash Memory Emulation in RAM ............................................................................
19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 807 19.3 Medium-Speed Mode........................................................................................................ 807 19.4 Sleep Mode ....................................................................................................................... 808 19.5 Module Stop Mode............................................................................................................
20.3.6 Flash Memory Characteristics ............................................................................. 860 20.3.7 Usage Note (Internal voltage step down for the H8S/2319C F-ZTAT) ............... 861 20.4 Usage Note........................................................................................................................ 861 Appendix A Instruction Set ...............................................................................863 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .........
Rev.7.00 Feb.
Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2319 Group is a series of microcomputer (MCU: microcomputer unit), built around the H8S/2000 CPU, employing Renesas's proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Section 1 Overview Table 1.
Section 1 Overview Item Specification 8-bit timer, 2 channels • 8-bit up-counter (external event count capability) • Two time constant registers • Two-channel connection possible Watchdog timer • Watchdog timer or interval timer selectable Serial communication interface (SCI), 2 channels • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Smart card interface function A/D converter • Resolution: 10 bits • Input: 8 channels • High-speed conver
Section 1 Overview Item Specification Power-down state • Medium-speed mode • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode • Variable clock division ratio • Eight MCU operating modes (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) Operating modes CPU Operating Description Mode Mode 1 — — External Data Bus On-Chip Initial Maximum ROM Value Value — — — 2 3 4 5 Advanced On-chip ROM disabled expansion mode 6 On-chip ROM enabled expans
Section 1 Overview Item Specification Operating modes • Four MCU operating modes (ROMless, mask ROM versions, H8S/2319 FZTAT, and H8S/2319C F-ZTAT) CPU Operating Description Mode Mode 1 1* 2 2* 2 3* 3 4* — — External Data Bus On-Chip Initial ROM Value Maximum Value — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 3 5* On-chip ROM disabled Disabled 8 bits 16 bits expansion mode 6 On-chip ROM enabled Enabled 8 bits 16 bits expansion mode 7 Single-chip mode Enabled — —
Section 1 Overview Item Specification Product lineup Condition A Condition B Operating power supply voltage 2.7 to 3.6 V 3.0 to 3.
Section 1 Overview Item Specification Other features • Differences between H8S/2319 F-ZTAT and H8S/2319C F-ZTAT ⎯ On-chip RAM H8S/2319 F-ZTAT: 8 kbytes (H'FFDC00 to H'FFFBFF) H8S/2319C F-ZTAT: 16 kbytes (H'FFBC00 to H'FFFBFF) ⎯ On-chip flash memory The H8S/2319 F-ZTAT and H8S/2319C F-ZTAT both have 512 kbytes of on-chip flash memory. However, the method for controlling the flash memory is different for the two LSIs.
Section 1 Overview PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/IRQ3 PF2/WAIT/IRQ2/DREQO PF1/BACK/IRQ1/CS5 PF0/BREQ/IRQ0/CS4 PG4/CS0 PG3/CS1/CS7 PG2/CS2 PG1/CS3/IRQ7/CS6 PG0/ADTRG/IRQ6 DTC 2 ROM* Port F Peripheral address bus Interrupt controller Peripheral data bus H8S/2000 CPU Bus controller PE7/ D7 PE6/ D6 PE5/ D5 PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 Port E Internal address bus Port D Internal data bus Clock pulse generator MD2 MD1 MD0 EXTAL XTAL STBY RES 1 WDTOVF (FWE, EMLE, VCL)* NMI PD7/ D15
XTAL VCC STBY NMI RES MD2 WDTOVF (FWE, EMLE, VCL)* P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF7/φ 65 PF6/AS 69 66 PF5/RD 70 VSS PF4/HWR 71 EXTAL PF3/LWR/IRQ3 72 67 PF2/WAIT/IRQ2/BREQO 73 Pin Arrangement PF1/BACK/IRQ1/CS5 1.3.1 74 Pin Description 75 1.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Vref AVCC PF0/BREQ/IRQ0/CS4 PF1/BACK/IRQ1/CS5 PF2/WAIT/IRQ2/BREQO PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/φ VSS EXTAL XTAL VCC STBY NMI RES MD2 WDTOVF (FWE, EMLE, VCL)* P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 PA0/A16 VSS Section 1 Overview 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Section 1 Overview MD0 P22/TIOCC3/TMRI0 P21/TIOCB3/TRST* 56 PA1/A17 MD1 57 PA2/A18 P23/TIOCD3/TMCI0 58 51 EMLE* 59 PA3/A19 MD2 60 52 RES 61 P20/TIOCA3/TMS* NMI 62 53 STBY 63 54 VCC 64 55 XTAL PF7/φ 69 65 PF6/AS 70 66 PF5/RD 71 VSS PF4/HWR 72 EXTAL PF3/LWR/IRQ3 73 67 PF2/WAIT/IRQ2/BREQO 74 68 PF1/BACK/IRQ1/CS5 75 E10A compatible version 34 PC2/A2 PG0/ADTRG/IRQ6 93 33 PC1/A1 PG1/CS3/IRQ7/CS6 94 32 PC0/A0 PG2/CS2 95 31 VSS PG3/CS1/CS7 96 30 PD7/D15 P
Section 1 Overview PA3/A19 PA2/A18 PA1/A17 PA0/A16 VSS P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3/TRST* P20/TIOCA3/TMS* 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Vref AVCC PF0/BREQ/IRQ0/CS4 PF1/BACK/IRQ1/CS5 PF2/WAIT/IRQ2/BREQO PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/φ VSS EXTAL XTAL VCC STBY NMI RES MD2 EMLE* E10A compatible version 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/
Section 1 Overview 1 2 3 4 5 6 7 8 9 10 11 A NC P11 PG3 PG2 P26 VSS P45 P41 VREF PF0 AVCC B P12 P10 VCC PG4 NC P27 AVSS P44 P42 PF2 PF1 C P13 P16 NC P14 PG1 PG0 P47 P43 NC PF3 PF4 D P15 VSS P17 NC P25 P24 P46 PF5 P40 NC PF7 E P30 P33 P32 P31 NC STBY VSS PF6 VCC F P34 PE2 PE3 P35 NMI EXTAL XTAL RES G PE1 PE5 VSS PE0 MD2 P23 H PE4 NC PD6 PE6 PC2 PC6 PC7 NC MD0 MD1 P21 J NC PD0 PE7 VSS PC3 PB1 PB2 P20 PB6
Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview 1.3.3 Table 1.3 Pin Functions Pin Functions Pin No. TFP-100B, TFP-100G FP-100A TLP-113V Type Symbol Power supply VCC 40, 65, 98 42, 67, 100 B3, E11, L7 Input Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. VSS 7, 18, 31, 49, 68, 88 9, 20, 33, 51, 70, 90 A6, D2, E9, Input G3, J4, K3, K10 Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V).
Section 1 Overview Pin No. Type Symbol TFP-100B, TFP-100G FP-100A TLP-113V Operating mode control MD2 to MD0 61, 58, 57 63, 60, 59 G10, H10, H9 I/O Name and Function Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2319 Group is operating.
Section 1 Overview Pin No. Type Symbol TFP-100B, TFP-100G FP-100A TLP-113V Operating mode control MD2 to MD0 61, 58, 57 63, 60, 59 G10, H10, H9 I/O Name and Function Input • Mask ROM and ROMless versions, H8S/2319 F-ZTAT, and H8S/2319C F-ZTAT MD2 MD1 MD0 Operating Mode 0 0 1 Mode 1*1 1 0 Mode 2*2 1 Mode 2*2 0 Mode 4*3 1 Mode 5*3 0 Mode 6 1 Mode 7 1 0 1 System control RES 62 64 F11 Input Reset input: When this pin is driven low, the chip is reset.
Section 1 Overview Pin No. Type Symbol TFP-100B, TFP-100G FP-100A TLP-113V I/O Name and Function Interrupts NMI 63 65 F8 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high.
Section 1 Overview Pin No. Type Symbol TFP-100B, TFP-100G FP-100A TLP-113V I/O Name and Function Bus control WAIT 74 76 B10 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state access space. 6, 4, 2, 1 8, 6, 4, 3 D3, D1, C1, B1 Input Clock input D to A: These pins input an external clock.
Section 1 Overview Pin No. TFP-100B, TFP-100G FP-100A TLP-113V Type Symbol Watchdog timer (WDT) WDTOVF*6 60 I/O Name and Function 62 G9 Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Serial communication interface (SCI) Smart Card interface TxD1, TxD0 9, 8 11, 10 E4, E1 Output Transmit data (channel 0, 1): Data output pins. RxD1, RxD0 11, 10 13, 12 E2, E3 Input Receive data (channel 0, 1): Data input pins.
Section 1 Overview Pin No. Type Symbol TFP-100B, TFP-100G FP-100A TLP-113V I/O ports P17 to P10 6 to 1, 100, 8 to 1 99 D3, C2, D1, I/O C4, C1, B1, A2, B2 Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). P27 to P20 92 to 89, 59, 56 to 54 94 to 91, 61, 58 to 56 B6, A5, D5, I/O D6, G11, J10, H11, J8 Port 2: An 8-bit I/O port.
Section 1 Overview Pin No. TFP-100B, TFP-100G FP-100A TLP-113V I/O Name and Function PF7 to PF0 69 to 76 71 to 78 D11, E10, D8, C11, C10, B10, B11, A10 I/O Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PG4 to PG0 97 to 93 99 to 95 B4, A3, A4, I/O C5, C6 Type Symbol I/O ports Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR).
Section 1 Overview Rev.7.00 Feb.
Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (4-Gbyte architecturally) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate : 25 MHz ⎯ 8/16/32-bit register-register add/subtract : 40 ns ⎯ 8 × 8-bit register-register multiply : 480 ns ⎯ 16 ÷ 8-bit register-register divide : 480 ns ⎯ 16 × 16-bit register-register multiply : 800 ns ⎯ 32 ÷ 16-bit register-register divide : 800 ns • CPU operating mode ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock sp
Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space ⎯ Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing ⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2319 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.1). For details of the exception vector table, see section 4, Exception Handling.
Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Section 2 CPU 2.3 Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (4-Gbyte architecturally) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2319 Group H'FFFFFFFF Advanced Mode Figure 2.3 Memory Map Rev.7.00 Feb.
Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers.
Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
Section 2 CPU 2.5.1 General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 7 6 5 4 3 2 1 0 Don't care Don't care 7 0 7 6 5 4 3 2 1 0 1-bit data 4-bit BCD data RnL RnH 4 3 7 Upper 4-bit BCD data 0 Lower Don't care RnL Byte data RnH 4 3 7 Upper Don't care 7 0 Lower 0 Don't care MSB Byte data LSB RnL 7 0 Don't care MSB LSB Figure 2.7 General Register Data Formats Rev.7.00 Feb.
Section 2 CPU Data Type Register Number Word data Rn Word data En Data Format 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats (cont) Rev.7.00 Feb.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.
Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
Section 2 CPU Table 2.3 Instructions Classified by Function 1 Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2319 Group. MOVTPE B Cannot be used in the H8S/2319 Group. POP W/L @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Section 2 CPU 1 Type Instruction Size* Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU 1 Type Instruction Size* Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU 1 Type Instruction Size* Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
Section 2 CPU 1 Type Instruction Size* Function Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
Section 2 CPU 1 Type Instruction Size* Function Bitmanipulation instructions BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Type Instruction Size Function Branch instructions Bcc — Branches to a specified relative address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Type Instruction 1 Size* Function System control TRAPA instructions RTE — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Type Instruction Size Function Block data transfer instruction EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6.
Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction.
Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Section 2 CPU If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address (For further information, see section 2.5.2, Memory Data Formats). 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. Rev.7.00 Feb.
4 3 rm rn r r disp r op r · Register indirect with pre-decrement @−ERn op Register indirect with post-increment or pre-decrement · Register indirect with post-increment @ERn+ op Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) op Register indirect (@ERn) op Register direct (Rn) Addressing Mode and Instruction Format disp 1 2 4 0 1, 2, or 4 General register contents Byte Word Longword 0 0 0 0 1, 2, or 4 General register contents Sign extension General register
Rev.7.00 Feb. 14, 2007 page 60 of 1108 REJ09B0089-0700 6 op op abs abs abs op IMM Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation 24 23 24 23 24 23 24 23 87 16 15 Sign extension H'FFFF Operand is immediate data.
8 7 No. op abs · Advanced mode Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format 31 31 Memory contents H'000000 87 disp PC contents Sign extension 23 23 abs Effective Address Calculation 0 0 0 0 24 23 24 23 Don't care 31 Don't care 31 Effective Address (EA) 0 0 Section 2 CPU Rev.7.00 Feb.
Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 1 Bus-released state End of exception handling SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1.
Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.
Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2.
Section 2 CPU Advanced mode SP SP EXR Reserved* CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Note: * Ignored when returning. Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU.
Section 2 CPU bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 19, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction.
Section 2 CPU Bus cycle T1 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.14 On-Chip Memory Access Cycle Bus cycle T1 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.15 Pin States during On-Chip Memory Access Rev.7.00 Feb.
Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access timing for the on-chip supporting modules. Figure 2.17 shows the pin states.
Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 Usage Note 2.10.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT) The H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT have eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3.1. Table 3.
Section 3 MCU Operating Modes The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes.
Section 3 MCU Operating Modes Table 3.2 MCU Operating Mode Selection (Mask ROM, ROMless versions, H8S/2319 FZTAT, and H8S/2319C F-ZTAT) External Data Bus CPU MCU Operating Operating Description MD2 MD1 MD0 Mode Mode 1 1* 2 2* 3 0 0 1 1 0 *2 3 4* 7 — Max.
Section 3 MCU Operating Modes only be used in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.3 Register Configuration The H8S/2319 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and system control register 2 (SYSCR2)*2 that control the operation of the chip. Table 3.3 summarizes these registers. Table 3.
Section 3 MCU Operating Modes Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 3.2.
Section 3 MCU Operating Modes Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD Description 0 PF3 is designated as LWR output pin 1 PF3 is designated as I/O port, and does not function as LWR output pin (Initial value) Bit 1—Reserved: Only 0 should be written to this bit. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode.
Section 3 MCU Operating Modes Bit 3 FLSHE 0 Description H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT • Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) H8S/2319C F-ZTAT • Flash control registers are not selected for addresses H'FFFFC4 to H'FFFFCF 1 H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT • Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB H8S/2319C F-
Section 3 MCU Operating Modes 3.3.3 Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only) This is a flash memory boot mode. See section 17, ROM, for details. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single chip mode. 3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Section 3 MCU Operating Modes 3.3.6 Mode 6 (Expanded Mode with On-Chip ROM Enabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, ports A, B, and C function as input ports immediately after a reset. These pins can be set to output addresses by setting the corresponding data direction register (DDR) bits and A23E to A20E in PFCR1 to 1. Port D functions as a data bus, and part of port F carries bus control signals.
Section 3 MCU Operating Modes 3.3.11 Modes 12 and 13 Modes 12 and 13 are not supported in the H8S/2319 Group, and must not be set. 3.3.12 Mode 14 (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT Only) This is a flash memory user program mode. For details, see section 17, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled. 3.3.
Section 3 MCU Operating Modes Table 3.
Section 3 MCU Operating Modes Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 3 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ reserved area*2 *4 On-chip ROM/ external address space*1 H'07FFFF H'080000 H'FF7400 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF External address space Reserved area*4 On-chip RAM*3 External address space Internal I/O registers External address space Internal I/O registers H'FF7
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'010000 External address space On-chip ROM/ external address space*1 External address space On-chip ROM/ reserved area*2 *5 H'07FFFF H'080000 H'080000 On-chip ROM External address space H'FF7400 Reserved area*4 H'FF7400 Reserved area*4 H'FF7400 H'FFDC00
Section 3 MCU Operating Modes Mode 1 User Boot Mode (advanced single-chip mode) H'000000 Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'000000 On-chip ROM On-chip ROM/ reserved area*2 *4 On-chip ROM/ reserved area*2 *4 On-chip ROM/ external address space*1 H'080000 H'080000 Reserved area*4 H'0FFFFF On-chip ROM H'010000 H'010000 H'080000 Mode 3 Boot Mode (advanced single-chip mode) Reserved area Reserved area*4 *4 H'0FFFFF H'100000 External addres
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 External address space H'080000 On-chip ROM/ reserved area*2 *4 H'080000 Reserved area*4 Reserved area*4 H'0FFFFF H'100000 External address space H'FF7400 Reserved area*4 H'FF7400 Reserved area*4 H'FF
Section 3 MCU Operating Modes Modes 4 and 5*1 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*2 On-chip ROM/ reserved area*3 *5 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*4 H'FFDC00 On-chip RAM*4 On-chip RAM H'FFFBFF H'FFFC00 External address s
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip RAM*3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H
Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip RAM *3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Intern
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 H'020000 On-chip ROM/ reserved area*2 *4 H'020000 Reserved area*4/external address space*1 Reserved area*4 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*3
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ reserved area*2 *4 On-chip ROM/ external address space*1 H'020000 H'020000 area*4/ Reserved external address space*1 Reserved area*4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip On-chip RAM*3 RAM*3 H'FFFBFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Ext
Section 3 MCU Operating Modes Mode 14 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ reserved area*2 *4 On-chip ROM/ external address space*1 H'020000 H'020000 area*4/ Reserved external address space*1 Reserved area*4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip On-chip RAM*3 RAM*3 H'FFFBFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Ext
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space H'010000 On-chip ROM H'010000 Reserved area*3/ external address space*1 Reserved area*3 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*2 H'FFDC00 On-chip RAM*2 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE5
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'010000 External address space H'060000 Reserved area*4 On-chip ROM/ external address space*1 H'060000 External address space H'FFDC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Interna
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 H'060000 Reserved area*4 H'080000 On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF Reserved area*4 External address space H'FFDC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Inte
Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 H'060000 Reserved area*4 H'080000 On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF Reserved area*4 External address space H'FFDC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address sp
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'010000 External address space H'060000 Reserved area*4 On-chip ROM/ external address space*1 H'060000 Reserved area*4 H'080000 H'080000 On-chip ROM External address space On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF External address space H'FFDC00 R
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 H'060000 Reserved area*4 H'080000 On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF Reserved area*4 External address space H'FFDC00 Reserved area*5 H'FFEC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External a
Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 H'060000 Reserved area*4 H'080000 On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF Reserved area*4 External address space H'FFDC00 Reserved area*5 H'FFEC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'
Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state.
Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. A reset can also be caused by watchdog timer overflow.
Section 4 Exception Handling Vector fetch φ Internal Prefetch of first processing program instruction * * * (1) (3) (5) RES Address bus RD High HWR, LWR (2) D15 to D0 (1), (3) (2), (4) (5) (6) (4) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception vector address) Start address ((5) = (2), (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.2 Reset Sequence (Mode 4) 4.2.
Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.
Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 43 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), and A/D converter.
Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.
Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.
Section 4 Exception Handling Rev.7.00 Feb.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. The available interrupt sources are external interrupts (NMI, IRQ7 to IRQ0) and internal interrupts (43 sources).
Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1.
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input 5.1.4 Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected Register Configuration Table 5.
Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating Modes.
Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 R/W — R/W R/W R/W — R/W R/W R/W : The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3.
Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected.
Section 5 Interrupt Controller 5.2.
Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode.
Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.
Section 5 Interrupt Controller Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR bit to 0 and use the pin as an I/O pin for another function. 5.3.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Origin of Interrupt Source DTC Priority Activation Vector Number Vector Address* 24 H'0060 IPRC2 to High IPRC0 WOVI (interval timer) Watchdog timer 25 H'0064 IPRD6 to IPRD4 — Reserved — 26 H'0068 IPRD2 to IPRD0 — Reserved — 27 H'006C IPRE6 to IPRE4 — ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to IPRE0 Reserved — 29 H'0074 30 H'0078 31 H'007C 32 H'0080 TGI0B (TGR0B input capture/compare match) 33 H'0084 TGI0C (TGR0C input capture/comp
Section 5 Interrupt Controller Origin of Interrupt Source DTC Priority Activation Vector Number Vector Address* 40 H'00A0 TGI1B (TGR1B input capture/compare match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 — TCI1U (underflow 1) 43 H'00AC — 44 H'00B0 45 H'00B4 Interrupt Source TGI1A (TGR1A input capture/compare match) TGI2A (TGR2A input capture/compare match) TPU channel 1 TPU channel 2 TGI2B (TGR2B input capture/compare match) IPR IPRF2 to IPRF0 High IPRG6 to IPRG4 TCI2V (overflow
Section 5 Interrupt Controller Origin of Interrupt Source DTC Priority Activation Vector Number Vector Address* 56 H'00E0 TGI4B (TGR4B input capture/compare match) 57 H'00E4 TCI4V (overflow 4) 58 H'00E8 — TCI4U (underflow 4) 59 H'00EC — 60 H'00F0 TGI5B (TGR5B input capture/compare match) 61 H'00F4 TCI5V (overflow 5) 62 H'00F8 — TCI5U (underflow 5) 63 H'00FC — 64 H'0100 CMIB0 (compare match B) 65 H'0104 OVI0 (overflow 0) 66 H'0108 — — Interrupt Source TGI4A (TGR4A input
Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector Number Vector Address* Reserved — 72 H'0120 73 H'0124 74 H'0128 75 H'012C 76 H'0130 77 H'0134 78 H'0138 79 H'013C 80 H'0140 RXI0 (receive-data-full 0) 81 H'0144 TXI0 (transmit-dataempty 0) 82 H'0148 TEI0 (transmit end 0) 83 H'014C 84 H'0150 RXI1 (receive-data-full 1) 85 H'0154 TXI1 (transmit-dataempty 1) 86 H'0158 TEI1 (transmit end 1) 87 H'015C 88 H'0160 89 H'0164 90 H'0168 9
Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.
Section 5 Interrupt Controller 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.
Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No I = 0? Hold pending Yes No IRQ0? Yes IRQ1? No Yes TEI1? Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.7.00 Feb.
Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Section 5 Interrupt Controller Program execution state Interrupt generated? No Yes Yes NMI? No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Mask level 5 or below? Level 1 interrupt? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.7.00 Feb.
Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.7.00 Feb.
Rev.7.00 Feb. 14, 2007 page 132 of 1108 REJ09B0089-0700 Figure 5.7 Interrupt Exception Handling (1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2), (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.
Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed.
Section 5 Interrupt Controller 5.6 DTC Activation by Interrupt 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 7, Data Transfer Controller. 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC and interrupt controller.
Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: For interrupt sources, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
Section 5 Interrupt Controller Usage Note: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. Rev.7.00 Feb.
Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The chip has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 Internal address bus Area decoder ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller WAIT Wait controller Internal control signals Internal data bus BREQO Bus mode signal WCRH WCRL CPU bus request signal Bus arbiter DTC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev.7.00 Feb.
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled.
Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.
Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Modes 5 to 7 Initial value : R/W : Mode 4 Initial value : R/W : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space.
Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode.
Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Section 6 Bus Controller WCRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Section 6 Bus Controller Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Section 6 Bus Controller Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access (Initial value) Bits 2 to 0—Reserved: Only 0 should be written to these bits. 6.2.
Section 6 Bus Controller Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access. Bit 6 BREQOE Description 0 BREQO output disabled.
Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 shows an outline of the area partitioning. Chip select signals (CS0 to CS7) can be output for each area.
Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWCR ABWn ASTCR ASTn Wn1 Wn0 Bus Width Program Wait Access States States 0 0 — — 16 2 0 1 0 0 3 0 1 1 1 0 2 1 1 0 — — 1 0 0 1 6.3.
Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 6.4, Basic Bus Interface, 6.5, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM*, and in ROM-disabled expansion mode, all of area 0 is external space.
Section 6 Bus Controller 6.3.5 Chip Select Signals The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR), CS167 Enable (CS167E), CS25 Enable, CSS17, CSS36, PF1CS5S, PF0CS4S for the port corresponding to the particular CSn pin.
Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd.
Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space Rev.7.00 Feb.
Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.7.00 Feb.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.7.00 Feb.
Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.7.00 Feb.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.7.00 Feb.
Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the H8S/2319 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. Rev.7.00 Feb.
Section 6 Bus Controller 6.5 Burst ROM Interface 6.5.1 Overview With the chip, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only.
Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.7.00 Feb.
Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6.15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control.
Section 6 Bus Controller 6.6 Idle Cycle 6.6.1 Operation When the chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and highspeed memory, I/O interfaces, and so on.
Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data.
Section 6 Bus Controller Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
Section 6 Bus Controller 6.6.2 Pin States in Idle Cycle Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 CSn* High impedance AS High RD High HWR High LWR High High Note: * n = 0 to 7 Rev.7.00 Feb.
Section 6 Bus Controller 6.7 Bus Release 6.7.1 Overview The chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, it can issue a bus request off-chip. 6.7.
Section 6 Bus Controller 6.7.3 Pin States in External Bus Released State Table 6.6 shows the pin states in the external bus released state. Table 6.6 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 CSn* High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance High impedance Note: * n = 0 to 7 Rev.7.00 Feb.
Section 6 Bus Controller 6.7.4 Transition Timing Figure 6.19 shows the timing for transition to the bus released state. CPU cycle T0 CPU cycle External bus released state T1 T2 φ High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [5] [6] [1] Low level of BREQ pin is sampled at rise of T2 state.
Section 6 Bus Controller 6.7.5 Usage Note Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a transition is made to sleep mode when either of these settings has been made. 6.8 Bus Arbitration 6.8.1 Overview The chip has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Section 6 Bus Controller 6.8.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request.
Section 6 Bus Controller Rev.7.00 Feb.
Section 7 Data Transfer Controller Section 7 Data Transfer Controller 7.1 Overview The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software. 7.1.
Section 7 Data Transfer Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Section 7 Data Transfer Controller 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.
Section 7 Data Transfer Controller 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode.
Section 7 Data Transfer Controller Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 Description 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Section 7 Data Transfer Controller Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit.
Section 7 Data Transfer Controller 7.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 ––– 4 3 2 1 0 ––– Initial value : R/W : ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.
Section 7 Data Transfer Controller transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 7.2.
Section 7 Data Transfer Controller Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description 0 DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] 1 • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that
Section 7 Data Transfer Controller Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software.
Section 7 Data Transfer Controller Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14 Description 0 DTC module stop mode cleared 1 DTC module stop mode set 7.3 Operation 7.3.1 Overview (Initial value) When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory.
Section 7 Data Transfer Controller Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No Yes No Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 7.2 Flowchart of DTC Operation Rev.7.00 Feb.
Section 7 Data Transfer Controller Table 7.
Section 7 Data Transfer Controller Table 7.
Section 7 Data Transfer Controller 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Section 7 Data Transfer Controller Source flag clearance Clear control Clear DTCER Clear request On-chip supporting module IRQ interrupt Interrupt request Selection circuit Select DTVECR DTC Interrupt controller CPU Interrupt mask Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect.
Section 7 Data Transfer Controller Table 7.
Section 7 Data Transfer Controller Origin of Interrupt Source Vector Number Vector Address DTCE* Priority TPU channel 3 48 H'0460 DTCEC5 High TGI3B (GR3B compare match/ input capture) 49 H'0462 DTCEC4 TGI3C (GR3C compare match/ input capture) 50 H'0464 DTCEC3 TGI3D (GR3D compare match/ input capture) 51 H'0466 DTCEC2 56 H'0470 DTCEC1 57 H'0472 DTCEC0 60 H'0478 DTCED5 61 H'047A DTCED4 Interrupt Source TGI3A (GR3A compare match/ input capture) TGI4A (GR4A compare match/ inpu
Section 7 Data Transfer Controller DTC vector address Register information start address Register information Next transfer Figure 7.4 Correspondence between DTC Vector Address and Register Information 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).
Section 7 Data Transfer Controller 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.6 lists the register information in normal mode and figure 7.6 shows the memory map in normal mode. Table 7.
Section 7 Data Transfer Controller 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.
Section 7 Data Transfer Controller 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified.
Section 7 Data Transfer Controller First block SAR or DAR Block area DAR or SAR Transfer Nth block Figure 7.8 Memory Map in Block Transfer Mode Rev.7.00 Feb.
Section 7 Data Transfer Controller 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows the memory map for chain transfer.
Section 7 Data Transfer Controller 7.3.9 Operation Timing Figures 7.10 to 7.12 show examples of DTC operation timing. φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.
Section 7 Data Transfer Controller φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Example of Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.9 lists execution phases for a single DTC data transfer, and table 7.10 shows the number of states required for each execution phase. Table 7.
Section 7 Data Transfer Controller Table 7.
Section 7 Data Transfer Controller 7.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 7 Data Transfer Controller 7.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 7 Data Transfer Controller Chain Transfer when Counter = 0: By executing a second data transfer, and performing resetting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 7.13 shows the memory map. [1] For the first transfer, set the normal mode for input data.
Section 7 Data Transfer Controller Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 7.13 Chain Transfer when Counter = 0 Rev.7.00 Feb.
Section 7 Data Transfer Controller Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Section 7 Data Transfer Controller 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Section 7 Data Transfer Controller Rev.7.00 Feb.
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The H8S/2319 Group has 10 I/O ports (ports 1 to 3, and A to G), and one input-only port (port 4). Table 8.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only ports), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Section 8 I/O Ports Table 8.
Section 8 I/O Ports Port Description Pins Mode 4 Mode 5 Mode 6*1 Mode 7*1 Port 4 • 8-bit input port P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1 and DA0) Port A • 4-bit I/O port PA3/A19 to PA0/A16 Address output • Built-in MOS input pull-up • Open-drain output capability Port B • 8-bit I/O port When DDR = I/O port 0 (after reset): input ports When DDR
Section 8 I/O Ports Port Description Port E • 8-bit I/O port Pins PE7/D7 to PE0/D0 • Built-in MOS input pull-up Port F • 8-bit I/O port Mode 4 Mode 5 Mode 6*1 In 8-bit bus mode: I/O port Mode 7*1 I/O port In 16-bit bus mode: data bus input/output PF7/φ • Schmitttriggered input (IRQ3 to IRQ0) When DDR = 0: input port When DDR = 1 (after reset): φ output When DDR = 0 (after reset): input port When DDR = 1: φ output PF6/AS When ASOD = 1: I/O port I/O port When ASOD = 0: AS output PF5/RD PF4/
Section 8 I/O Ports Port Description Port G • 5-bit I/O port • Schmitttriggered input (IRQ7, IRQ6) Pins PG4/CS0 PG3/CS1/CS7 PG2/CS2 Mode 4 Mode 5 Mode 6*1 Mode 7*1 When DDR = 0*2: input port When DDR = 1*3: CS0 output I/O port also functions as interrupt I/O port input pins When DDR = 1, CS167E = 1, and CSS17 (IRQ7, IRQ6) and A/D = 0: Also functions as CS1 output converter When DDR = 1, CS167E = 1, and CSS17 input pin = 1: Also functions as CS7 output (ADTRG) I/O port When DDR = 1 and CS25E = 1:
Section 8 I/O Ports 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and an address bus output function. Port 1 pin functions change according to the operating mode. The address output or port output function is selected according to the settings of bits A23E to A20E in PFCR1. Port 1 pins have Schmitt-trigger inputs. Figure 8.
Section 8 I/O Ports 8.2.2 Register Configuration Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbreviation R/W Initial Value Address* Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Port function control register 1 PFCR1 R/W H'0F H'FF45 Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port 1 Data Register (P1DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Port Function Control Register 1 (PFCR1) Bit : 7 CSS17 Initial value : R/W : 6 5 4 CSS36 PF1CS5S PF0CS4S 3 2 1 0 A23E A22E A21E A20E 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For details, see section 8.12, Port G.
Section 8 I/O Ports Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). This bit is valid in modes 4 to 6. Bit 1 A21E Description 0 P11DR is output when P11DDR = 1 1 A21 is output when P11DDR = 1 (Initial value) Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). This bit is valid in modes 4 to 6. Bit 0 A20E Description 0 P10DR is output when P10DDR = 1 1 A20 is output when P10DDR = 1 Rev.7.00 Feb.
Section 8 I/O Ports 8.2.3 Pin Functions Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and address output pins (A23 to A20). Port 1 pin functions are shown in table 8.3. Table 8.
Section 8 I/O Ports Pin Selection Method and Pin Functions P16/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, and bit P16DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P15/TIOCB1/ TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, and bit P15DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P14/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, and bit P14DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P13/TIOCD0/ TCLKB/A23 The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit A23E in PFCR1, and bit P13DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P12/TIOCC0/ TCLKA/A22 The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit A22E in PFCR1 and bit P12DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P11/TIOCB0/ A21 The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A21E in PFCR1 and bit P11DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P10/TIOCA0/ A20 The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A20E in PFCR1 and bit P10DDR.
Section 8 I/O Ports 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 8.2 shows the port 2 pin configuration.
Section 8 I/O Ports Port 2 Data Direction Register (P2DDR) Bit : 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Section 8 I/O Ports Port 2 Register (PORT2) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P27 —* P26 —* P25 —* P24 —* P23 —* P22 —* P21 —* P20 —* R R R R R R R R Note: * Determined by state of pins P27 to P20. PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read.
Section 8 I/O Ports 8.3.3 Pin Functions Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 8.5. Table 8.
Section 8 I/O Ports Pin Selection Method and Pin Functions P26/TIOCA5/ TMO0 The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR0, and bit P26DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P25/TIOCB4/ TMCI1 This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P25DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P24/TIOCA4/ TMRI1 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P24DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P23/TIOCD3/ TMCI0 This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P23DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P22/TIOCC3/ TMRI0 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P22DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P21/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P21DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P20/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P20DDR.
Section 8 I/O Ports 8.4 Port 3 8.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are the same in all operating modes. The interrupt input pins (IRQ4, IRQ5) are Schmitt-triggered inputs. Figure 8.3 shows the port 3 pin configuration.
Section 8 I/O Ports Port 3 Data Direction Register (P3DDR) Bit : 7 6 — — 5 4 3 2 1 0 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : Undefined Undefined 0 0 0 0 0 0 R/W W W W W W W : — — P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read.
Section 8 I/O Ports Port 3 Register (PORT3) Bit : 7 6 5 4 3 2 1 0 — — P35 —* P34 —* P33 —* P32 —* P31 —* P30 —* R R R R R R Initial value : Undefined Undefined R/W : — — Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR.
Section 8 I/O Ports 8.4.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are shown in table 8.7. Table 8.7 Port 3 Pin Functions Pin Selection Method and Pin Functions P35/SCK1/IRQ5 The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE 0 P33DDR Pin function 1 0 1 — P33 input pin P33 output pin* RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR.
Section 8 I/O Ports 8.5 Port 4 8.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 8.4 shows the port 4 pin configuration.
Section 8 I/O Ports 8.5.2 Register Configuration Table 8.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 8.8 Port 4 Register Name Abbreviation R/W Initial Value Address* Port 4 register PORT4 R Undefined H'FF53 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Section 8 I/O Ports 8.6 Port A 8.6.1 Overview Port A is a 4-bit I/O port. Port A pins also function as address bus outputs. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 8.5 shows the port A pin configuration.
Section 8 I/O Ports 8.6.2 Register Configuration Table 8.9 shows the port A register configuration. Table 8.9 Port A Registers 1 2 Name Abbreviation R/W Initial Value* Address* Port A data direction register PADDR W H'0 H'FEB9 Port A data register PADR R/W H'0 H'FF69 Port A register PORTA R Undefined H'FF59 Port A MOS pull-up control register PAPCR R/W H'0 H'FF70 Port A open-drain control register PAODR R/W H'0 H'FF77 Notes: 1. Value of bits 3 to 0. 2.
Section 8 I/O Ports • Mode 7* Setting PADDR bits to 1 makes the corresponding port A pins output ports, while clearing the bits to 0 makes the pins input ports. Note: * Modes 6 and 7 are not available in the ROMless versions.
Section 8 I/O Ports Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 6 5 4 — — — — Initial value : Undefined Undefined Undefined Undefined R/W : — — — — 3 2 1 0 PA3PCR PA2PCR PA1PCR PA0PCR 0 0 0 0 R/W R/W R/W R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
Section 8 I/O Ports 8.6.3 Pin Functions Modes 4 and 5: In modes 4 and 5, the lower 4 bits of port A are designated as address outputs automatically. Port A pin functions in modes 4 and 5 are shown in figure 8.6. A19 (output) A18 (output) Port A A17 (output) A16 (output) Figure 8.6 Port A Pin Functions (Modes 4 and 5) Mode 6*: In mode 6*, port A pins function as address outputs or input ports. Input or output can be specified on an individual bit basis.
Section 8 I/O Ports PA3 (I/O) PA2 (I/O) Port A PA1 (I/O) PA0 (I/O) Figure 8.8 Port A Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available in the ROMless versions. 8.6.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7*, and cannot be used in modes 4 and 5. MOS input pull-up can be specified as on or off on an individual bit basis.
Section 8 I/O Ports 8.7 Port B 8.7.1 Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 8.9 shows the port B pin configuration.
Section 8 I/O Ports 8.7.2 Register Configuration Table 8.11 shows the port B register configuration. Table 8.11 Port B Registers Name Abbreviation R/W Initial Value Address* Port B data direction register PBDDR W H'00 H'FEBA Port B data register PBDR R/W H'00 H'FF6A Port B register PORTB R Undefined H'FF5A Port B MOS pull-up control register PBPCR R/W H'00 H'FF71 Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port B Data Register (PBDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis.
Section 8 I/O Ports Mode 6*: In mode 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting PBDDR bits to 1 makes the corresponding port B pins address outputs, while clearing the bits to 0 makes the pins input ports. Port B pin functions in mode 6 are shown in figure 8.
Section 8 I/O Ports 8.7.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When PBDDR bits are cleared to 0 in mode 6 or 7, setting the corresponding PBPCR bits to 1 turns on the MOS input pull-up for that pins. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 8 I/O Ports 8.8 Port C 8.8.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 8.13 shows the port C pin configuration.
Section 8 I/O Ports 8.8.2 Register Configuration Table 8.13 shows the port C register configuration. Table 8.13 Port C Registers Name Abbreviation R/W Initial Value Address* Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC R Undefined H'FF5B Port C MOS pull-up control register PCPCR R/W H'00 H'FF72 Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port C Data Register (PCDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis.
Section 8 I/O Ports Mode 6*: In mode 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting PCDDR bits to 1 makes the corresponding port C pins address outputs, while clearing the bits to 0 makes the pins an input ports. Port C pin functions in mode 6 are shown in figure 8.15.
Section 8 I/O Ports 8.8.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When PCDDR bits are cleared to 0 in mode 6 or 7, setting the corresponding PCPCR bits to 1 turns on the MOS input pull-up for that pins. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 8 I/O Ports 8.9 Port D 8.9.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 8.17 shows the port D pin configuration.
Section 8 I/O Ports 8.9.2 Register Configuration Table 8.15 shows the port D register configuration. Table 8.15 Port D Registers Name Abbreviation R/W Initial Value Address* Port D data direction register PDDDR W H'00 H'FEBC Port D data register PDDR R/W H'00 H'FF6C Port D register PORTD R Undefined H'FF5C Port D MOS pull-up control register PDPCR R/W H'00 H'FF73 Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port D Data Register (PDDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis.
Section 8 I/O Ports 8.9.3 Pin Functions Modes 4 to 6*: In modes 4 to 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 4 to 6 are shown in figure 8.18. D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 8.18 Port D Pin Functions (Modes 4 to 6) Mode 7*: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis.
Section 8 I/O Ports 8.9.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When PDDDR bits are cleared to 0 in mode 7, setting the corresponding PDPCR bits to 1 turns on the MOS input pull-up for that pins. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 8 I/O Ports 8.10 Port E 8.10.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 8.20 shows the port E pin configuration.
Section 8 I/O Ports 8.10.2 Register Configuration Table 8.17 shows the port E register configuration. Table 8.17 Port E Registers Name Abbreviation R/W Initial Value Address* Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D Port E MOS pull-up control register PEPCR R/W H'00 H'FF74 Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port E Data Register (PEDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis.
Section 8 I/O Ports Port E 8-bit bus mode 16-bit bus mode PE7 (I/O) D7 (I/O) PE6 (I/O) D6 (I/O) PE5 (I/O) D5 (I/O) PE4 (I/O) D4 (I/O) PE3 (I/O) D3 (I/O) PE2 (I/O) D2 (I/O) PE1 (I/O) D1 (I/O) PE0 (I/O) D0 (I/O) Figure 8.21 Port E Pin Functions (Modes 4 to 6) Mode 7*: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis.
Section 8 I/O Ports 8.10.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4, 5, and 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When PEDDR bits are cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bits to 1 turns on the MOS input pull-up for that pins.
Section 8 I/O Ports 8.11 Port F 8.11.1 Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5), the system clock (φ) output pin and interrupt input pins (IRQ0 to IRQ3). The interrupt input pins (IRQ0 to IRQ3) are Schmitt-triggered inputs. Figure 8.23 shows the port F pin configuration.
Section 8 I/O Ports 8.11.2 Register Configuration Table 8.19 shows the port F register configuration. Table 8.
Section 8 I/O Ports Port F Data Register (PFDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 8 I/O Ports Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For details, see section 8.12, Port G. Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For details, see section 8.12, Port G. Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output. This bit is valid in modes 4 to 6. Bit 5 PF1CS5S Description 0 PF1 is the PF1/BACK/IRQ1 pin 1 PF1 is the PF1/BACK/IRQ1/CS5 pin.
Section 8 I/O Ports Port Function Control Register 2 (PFCR2) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — CS167E CS25E ASOD — — — 0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bit 5—CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output.
Section 8 I/O Ports System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in modes 4 to 6.
Section 8 I/O Ports Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus-released state, or when an internal bus master performs an external space access. Bit 6 BREQOE Description 0 BREQO output disabled. BREQO pin can be used as I/O port 1 BREQO output enabled (Initial value) Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Section 8 I/O Ports 8.11.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5) the system clock (φ) output pin and interrupt input pins (IRQ0 to IRQ3). The pin functions differ between modes 4 to 6*1, and mode 7*1. Port F pin functions are shown in table 8.20. Table 8.20 Port F Pin Functions Pin Selection Method and Pin Functions PF7/φ The pin function is switched as shown below according to bit PF7DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PF3/LWR/IRQ3 The pin function is switched as shown below according to the operating mode, and bit PF3DDR, and bit LWROD in SYSCR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PF1/BACK/IRQ1/ CS5 The pin function is switched as shown below according to the operating mode, and the BRLE bit in BCRL, PF1CS5S bit in PFCR1, and CS25E bit in PFCR2 and PF1DDR bit.
Section 8 I/O Ports 8.12 Port G 8.12.1 Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7). The A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The interrupt input pins (IRQ6, IRQ7) are Schmitt-triggered inputs. Figure 8.24 shows the port G pin configuration.
Section 8 I/O Ports 8.12.2 Register Configuration Table 8.21 shows the port G register configuration. Table 8.21 Port G Registers 1 2 Name Abbreviation R/W Initial Value* Address* Port G data direction register PGDDR W H'10/H'00* H'FEBF Port G data register PGDR R/W H'00 H'FF6F Port G register PORTG R Undefined H'FF5F Port function control register 1 PFCR1 R/W H'0F H'FF45 Port function control register 2 PFCR2 R/W H'30 H'FFAC 3 Notes: 1. Value of bits 4 to 0. 2.
Section 8 I/O Ports Port G Data Register (PGDR) Bit : 7 6 5 4 3 2 1 0 — — — PG4DR PG3DR PG2DR PG1DR PG0DR 0 0 0 0 0 R/W R/W R/W R/W R/W Initial value : Undefined Undefined Undefined R/W : — — — PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode.
Section 8 I/O Ports Port Function Control Register 1 (PFCR1) Bit : 7 CSS17 Initial value : R/W : 6 5 4 CSS36 PF1CS5S PF0CS4S 3 2 1 0 A23E A22E A21E A20E 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin.
Section 8 I/O Ports Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see section 8.2, Port 1. Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see section 8.2, Port 1.
Section 8 I/O Ports 8.12.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7) the A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The pin functions are different in mode 7*1, and modes 4 to 6*1. Port G pin functions are shown in table 8.22. Table 8.22 Port G Pin Functions Pin Selection Method and Pin Functions PG4/CS0 The pin function is switched as shown below according to the operating mode and bit PG4DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PG1/CS3/CS6/ IRQ7 The pin function is switched as shown below according to the combination of operating mode and CSS36 bit in PFCR1, CS167E bit in PFCR2, CS25E bit and bit PG1DDR.
Section 8 I/O Ports Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) 9.1 Overview The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 9.1.
Section 9 16-Bit Timer Pulse Unit (TPU) • 26 interrupt sources ⎯ For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ⎯ For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently • Automatic transfer of register data ⎯ Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer control
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 lists the functions of the TPU. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture A/D conversion start trigger TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or in
Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.3 Pin Configuration Table 9.2 summarizes the TPU pins. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Name Symbol I/O Function 3 Input capture/out compare match A3 TIOCA3 I/O TGR3A input capture input/output compare output/PWM output pin Input capture/out compare match B3 TIOCB3 I/O TGR3B input capture input/output compare output/PWM output pin Input capture/out compare match C3 TIOCC3 I/O TGR3C input capture input/output compare output/PWM output pin Input capture/out compare match D3 TIOCD3 I/O TGR3D input capture input/output compare ou
Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.4 Register Configuration Table 9.3 summarizes the TPU registers. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 1 Channel Name Abbreviation R/W Initial Value Address* 3 Timer control register 3 TCR3 R/W H'00 H'FE80 Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84 Timer status register 3 TSR3 R/(W)* H'C0 H'FE85 Timer counter 3 TCNT3 R/W H'0000 H'FE86 Timer general register 3A TGR3A
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2 Register Descriptions 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source.
Section 9 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 (Initial value) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 De
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/1024 0 Internal clock: counts on φ/256 1 Internal clock: counts on φ/4096 1 1 0 1 (Initial value) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Inter
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 0 1 1 0 Description TGR0D Output disabled is output Initial output is 0 compare output 2 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D Capture input so
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 1 0 0 0 0 1 1 0 Description TGR1B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is input capture re
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 3 0 0 0 0 1 1 0 Description TGR3B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 Note: * 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR3B is input
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 3 0 0 0 0 1 1 0 Description TGR3D Output disabled is output Initial output is 0 compare output 2 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR3D Capture input so
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 4 0 0 0 0 1 1 0 Description TGR4B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4B is input capture re
Section 9 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 1 1 0 Description TGR0C Output disabled is output Initial output is 0 compare 1 output * register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 Note: * 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0C Capt
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 1 0 0 0 0 1 1 0 Description TGR1A Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is input capture r
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 3 0 0 0 0 1 1 0 Description TGR3A Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR3A is input capture r
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 3 0 0 0 0 1 1 0 Description TGR3C Output disabled is output Initial output is 0 compare 1 output * register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 Note: * 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR3C Capt
Section 9 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 4 0 0 0 0 1 1 0 Description TGR4A Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is input capture re
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU bit when the TCFU bit in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB Description 0 Interrupt requests (TGIB) by TGFB disabled 1 Interrupt requests (TGIB) by TGFB enabled (Initial value) Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.5 Timer Status Registers (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Initial value : 1 1 0 R/W — — — : Note: * Only 0 can be written, to clear the flag.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 6—Reserved: This bit cannot be modified and is always read as 1. Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA Description 0 [Clearing conditions] 1 (Initial value) • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.7 Bit Timer General Registers (TGR) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5.
Section 9 16-Bit Timer Pulse Unit (TPU) Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn Description 0 TCNTn count operation is stopped 1 TCNTn performs count operation (Initial value) n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit n SYNCn Description 0 TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) 1 TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 9.2.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3 Interface to Bus Master 9.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 9.2. Internal data bus H Bus master L Module data bus Bus interface TCNTH TCNTL Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of 8-bit register access operation are shown in figures 9.3 to 9.5. Internal data bus H Bus master L Module data bus Bus interface TCR Figure 9.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 9.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4 Operation 9.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 9.6 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR.
Section 9 16-Bit Timer Pulse Unit (TPU) • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 9 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 9.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) • Examples of waveform output operation Figure 9.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Section 9 16-Bit Timer Pulse Unit (TPU) • Example of input capture operation Figure 9.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 9.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing sources. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9.5 shows the register combinations used in buffer operation. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.17. Input capture signal Timer general register Buffer register TCNT Figure 9.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation • When TGR is an output compare register Figure 9.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 9 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register Figure 9.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.6 shows the register combinations used in cascaded operation.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 9.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Section 9 16-Bit Timer Pulse Unit (TPU) TCLKC TCLKD TCNT2 FFFD TCNT1 FFFE FFFF 0000 0000 0001 0002 0001 0001 0000 FFFF 0000 Figure 9.23 Example of Cascaded Operation (2) 9.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Section 9 16-Bit Timer Pulse Unit (TPU) The correspondence between PWM output pins and registers is shown in table 9.7. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 9.24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation: Figure 9.25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the value set in TGRB as the duty. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the period, and the values set in the other TGR registers as the duty.
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 9.29 shows an example of phase counting mode 1 operation, and table 9.9 summarizes the TCNT up/down-count conditions.
Section 9 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 2 Figure 9.30 shows an example of phase counting mode 2 operation, and table 9.10 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.30 Example of Phase Counting Mode 2 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 3 Figure 9.31 shows an example of phase counting mode 3 operation, and table 9.11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.31 Example of Phase Counting Mode 3 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 4 Figure 9.32 shows an example of phase counting mode 4 operation, and table 9.12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 9.32 Example of Phase Counting Mode 4 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 9.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Section 9 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) − TGR0C (position control period) + − TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 9.33 Phase Counting Mode Application Example 9.5 Interrupts 9.5.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.13 lists the TPU interrupt sources. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.6 Operation Timing 9.6.1 Input/Output Timing TCNT Count Timing: Figure 9.34 shows TCNT count timing in internal clock operation, and figure 9.35 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock TCNT N−1 N N+1 N+2 Figure 9.34 Count Timing in Internal Clock Operation φ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N−1 N N+1 Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.36 shows output compare output timing.
Section 9 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 9.38 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.39 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 9.38 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT N H'0000 N TGR Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 9.40 and 9.41 show the timing in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 9.40 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 9.41 Buffer Operation Timing (Input Capture) Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 9.42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 9.42 TGI Interrupt Timing (Compare Match) Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 9.43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 9.43 TGI Interrupt Timing (Input Capture) Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 9.44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 9.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.46 shows the timing for status flag clearing by the CPU, and figure 9.47 shows the timing for status flag clearing by the DTC. TSR write cycle T2 T1 φ Address TSR address Write signal Status flag Interrupt request signal Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.7 Usage Notes Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.49 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 9.49 Contention between TCNT Write and Clear Operations Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.50 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT input clock N TCNT M TCNT write data Figure 9.50 Contention between TCNT Write and Increment Operations Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 9.51 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9.52 shows the timing in this case. TGR write cycle T1 T2 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.53 shows the timing in this case. TGR read cycle T2 T1 φ TGR address Address Read signal Input capture signal TGR Internal data bus X M M Figure 9.53 Contention between TGR Read and Input Capture Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.54 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Input capture signal TCNT M M TGR Figure 9.54 Contention between TGR Write and Input Capture Rev.7.00 Feb.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.55 shows the timing in this case. Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT N M TGR Buffer register N M Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Prohibited TCFV flag Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M Prohibited TCFV flag Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Rev.7.00 Feb.
Section 10 8-Bit Timers Section 10 8-Bit Timers 10.1 Overview The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 10.1.1 Features The features of the 8-bit timer module are listed below.
Section 10 8-Bit Timers 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the 8-bit timer module.
Section 10 8-Bit Timers 10.1.3 Pin Configuration Table 10.1 summarizes the input and output pins of the 8-bit timer module. Table 10.
Section 10 8-Bit Timers 10.2 Register Descriptions 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 Bit TCNT1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source.
Section 10 8-Bit Timers The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 in TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 10.2.
Section 10 8-Bit Timers Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. Bit 7 CMIEB Description 0 CMFB interrupt requests (CMIB) are disabled 1 CMFB interrupt requests (CMIB) are enabled (Initial value) Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1.
Section 10 8-Bit Timers When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1.
Section 10 8-Bit Timers TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
Section 10 8-Bit Timers Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified.
Section 10 8-Bit Timers 10.2.6 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 10 8-Bit Timers 10.3 Operation 10.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N−1 N N+1 Figure 10.
Section 10 8-Bit Timers φ External clock input pin Clock input to TCNT TCNT N−1 N N+1 Figure 10.3 Count Timing for External Clock Input 10.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Section 10 8-Bit Timers Timer Output Timing: When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 10.
Section 10 8-Bit Timers 10.3.3 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N−1 N H'00 Figure 10.7 Timing of Clearance by External Reset 10.3.
Section 10 8-Bit Timers 10.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below.
Section 10 8-Bit Timers 10.4 Interrupts 10.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 10.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 10.
Section 10 8-Bit Timers 10.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match.
Section 10 8-Bit Timers 10.6 Usage Notes Note that the following kinds of contention can occur in the 8-bit timer module. 10.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 10.10 shows this operation.
Section 10 8-Bit Timers 10.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 10.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 10.11 Contention between TCNT Write and Increment Rev.7.00 Feb.
Section 10 8-Bit Timers 10.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 10.12 shows this operation. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Inhibited Figure 10.12 Contention between TCOR Write and Compare Match Rev.7.00 Feb.
Section 10 8-Bit Timers 10.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 10.4. Table 10.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 10.6.
Section 10 8-Bit Timers Table 10.5 Switching of Internal Clock and TCNT Operation No.
Section 10 8-Bit Timers No. 4 Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 10.6.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
Section 10 8-Bit Timers Rev.7.00 Feb.
Section 11 Watchdog Timer Section 11 Watchdog Timer 11.1 Overview The chip has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF)* if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the chip. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 11 Watchdog Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow WDTOVF*1 Internal reset signal*2 Clock Clock select Reset control RSTCSR Internal clock sources TCNT TSCR Module bus Bus interface WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: 1. The WDTOVF output function is not available in the F-ZTAT versions. 2.
Section 11 Watchdog Timer 11.1.3 Pin Configuration Table 11.1 describes the WDT output pin. Table 11.1 WDT Pin Name Symbol Watchdog timer overflow WDTOVF* Output I/O Function Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF function is not available in the F-ZTAT versions. 11.1.4 Register Configuration The WDT has three registers, as summarized in table 11.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 11.
Section 11 Watchdog Timer 11.2 Register Descriptions 11.2.1 Timer Counter (TCNT) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR.
Section 11 Watchdog Timer 11.2.2 Bit Timer Control/Status Register (TCSR) : Initial value : R/W : 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W — — R/W R/W R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode.
Section 11 Watchdog Timer Bit 6 WT/IT Description 0 Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) 1 Watchdog timer: Generates the WDTOVF signal* when TCNT overflows* 1 2 Notes: 1. The WDTOVF function is not available in the F-ZTAT versions. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Section 11 Watchdog Timer 11.2.3 Bit Reset Control/Status Register (RSTCSR) : Initial value : R/W : 7 6 5 4 3 2 1 0 WOVF RSTE — — — — — — 0 0 0 1 1 1 1 1 R/(W)* R/W R/W — — — — — Note: * Only 0 can be written, to clear the flag. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal.
Section 11 Watchdog Timer Bit 5—Reserved: This bit should be written with 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. 11.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
Section 11 Watchdog Timer Writing 0 to WOVF bit 15 8 7 H'A5 Address: H'FFBE 0 H'00 Writing to RSTE bit 15 Address: H'FFBE 8 7 H'5A 0 Write data Figure 11.3 Writing to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. 11.3 Operation 11.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1.
Section 11 Watchdog Timer TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF*3 and internal reset are generated WT/IT=1 TME=1 WDTOVF signal*3 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF output function is not available in the F-ZTAT versions. Figure 11.
Section 11 Watchdog Timer 11.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 11.5. This function can be used to generate interrupt requests at regular intervals.
Section 11 Watchdog Timer 11.3.3 Timing of Overflow Flag (OVF) Setting The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 11.6. φ TCNT H'FF Overflow signal (internal signal) OVF Figure 11.6 Timing of OVF Setting Rev.7.00 Feb.
Section 11 Watchdog Timer 11.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 11.7 shows the timing in this case. Note: * The WDTOVF output function is not available in the F-ZTAT versions.
Section 11 Watchdog Timer 11.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 11.5 Usage Notes 11.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
Section 11 Watchdog Timer 11.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors may occur in the incrementation.
Section 11 Watchdog Timer 11.5.5 Internal Reset in Watchdog Timer Mode The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag.
Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) 12.1 Overview The chip is equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 Features SCI features are listed below.
Section 12 Serial Communication Interface (SCI) • Full-duplex communication capability ⎯ The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • Choice of LSB-first or MSB-first transfer ⎯ Can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) • Buil
Section 12 Serial Communication Interface (SCI) 12.1.2 Block Diagram Bus interface Figure 12.1 shows a block diagram of the SCI.
Section 12 Serial Communication Interface (SCI) 12.1.3 Pin Configuration Table 12.1 shows the serial pins for each SCI channel. Table 12.
Section 12 Serial Communication Interface (SCI) 12.1.4 Register Configuration The SCI has the internal registers shown in table 12.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 12.
Section 12 Serial Communication Interface (SCI) 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 12.2.
Section 12 Serial Communication Interface (SCI) 12.2.3 Transmit Shift Register (TSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Section 12 Serial Communication Interface (SCI) 12.2.5 Bit Serial Mode Register (SMR) : Initial value : R/W : 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
Section 12 Serial Communication Interface (SCI) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Section 12 Serial Communication Interface (SCI) Bit 3 STOP Description 0 1 stop bit: In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 1 2 stop bits: In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting.
Section 12 Serial Communication Interface (SCI) 12.2.6 Bit Serial Control Register (SCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times.
Section 12 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
Section 12 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Section 12 Serial Communication Interface (SCI) Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode.
Section 12 Serial Communication Interface (SCI) 12.2.7 Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times.
Section 12 Serial Communication Interface (SCI) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Section 12 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER Description 0 [Clearing condition] 1 [Setting condition] 1 (Initial value)* When 0 is written to FER after reading FER = 1 When the SCI checks the stop bit at the end of the receive data when reception ends, 2 and the stop bit is 0 * Notes: 1.
Section 12 Serial Communication Interface (SCI) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
Section 12 Serial Communication Interface (SCI) 12.2.8 Bit Bit Rate Register (BRR) : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode.
Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ = 2 MHz φ = 2.097152 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 150 1 103 0.16 1 300 0 207 0.16 0 600 0 103 0.16 1200 0 51 2400 0 4800 φ = 2.4576 MHz N Error (%) –0.04 1 174 108 0.21 1 217 0.21 0 0 108 0.21 0 0.16 0 54 25 0.16 0 0 12 0.16 9600 0 6 19200 0 31250 38400 φ = 3 MHz N Error (%) –0.
Section 12 Serial Communication Interface (SCI) φ = 6 MHz Bit Rate (bits/s) n N Error (%) 110 2 106 150 2 300 φ = 6.144 MHz φ = 7.3728 MHz N Error (%) n N Error (%) –0.44 2 108 0.08 2 130 77 0.16 2 79 0.00 2 1 155 0.16 1 159 0.00 600 1 77 0.16 1 79 1200 0 155 0.16 0 2400 0 77 0.16 4800 0 38 0.16 9600 0 19200 0 31250 38400 φ = 8 MHz N Error (%) –0.07 2 141 0.03 95 0.00 2 103 0.16 1 191 0.00 1 207 0.16 0.00 1 95 0.00 1 103 0.
Section 12 Serial Communication Interface (SCI) φ = 14 MHz Bit Rate (bits/s) n N Error (%) 110 2 248 150 2 300 φ = 14.7456 MHz φ = 16 MHz φ = 17.2032 MHz N Error (%) n N Error (%) n N Error (%) –0.17 3 64 0.70 3 70 0.03 3 75 0.48 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.
Section 12 Serial Communication Interface (SCI) Table 12.4 BRR Settings for Various Bit Rates (Synchronous Mode) φ = 2 MHz Bit Rate (bits/s) n N 110 3 70 250 2 500 1 φ = 4 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz n N n N n N n N 124 2 249 3 124 — — 3 249 249 2 124 2 249 — — 3 124 φ = 20 MHz n N — — φ = 25 MHz n N 1k 1 124 1 249 2 124 — — 2 249 — — 3 97 2.
Section 12 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= φ 64 × 2 2n–1 ×B × 106 – 1 Synchronous mode: N= Where B: N: φ: n: φ 8×2 2n–1 ×B × 106 – 1 Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.
Section 12 Serial Communication Interface (SCI) Table 12.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.
Section 12 Serial Communication Interface (SCI) Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.
Section 12 Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7 12.2.
Section 12 Serial Communication Interface (SCI) Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level.
Section 12 Serial Communication Interface (SCI) 12.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 12 Serial Communication Interface (SCI) 12.3 Operation 12.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 12.8.
Section 12 Serial Communication Interface (SCI) Table 12.
Section 12 Serial Communication Interface (SCI) 12.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
Section 12 Serial Communication Interface (SCI) Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 12.
Section 12 Serial Communication Interface (SCI) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Section 12 Serial Communication Interface (SCI) Figure 12.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Start of initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made.
Section 12 Serial Communication Interface (SCI) Serial data transmission (asynchronous mode): Figure 12.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 12 Serial Communication Interface (SCI) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 12.
Section 12 Serial Communication Interface (SCI) Serial data reception (asynchronous mode): Figure 12.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 12 Serial Communication Interface (SCI) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 12.7 Sample Serial Reception Flowchart (cont) Rev.7.00 Feb.
Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks.
Section 12 Serial Communication Interface (SCI) Table 12.
Section 12 Serial Communication Interface (SCI) 12.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line.
Section 12 Serial Communication Interface (SCI) Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 12.
Section 12 Serial Communication Interface (SCI) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 12 Serial Communication Interface (SCI) Figure 12.11 shows an example of SCI operation for transmission using the multiprocessor format.
Section 12 Serial Communication Interface (SCI) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start of reception Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID.
Section 12 Serial Communication Interface (SCI) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.7.00 Feb.
Section 12 Serial Communication Interface (SCI) Figure 12.13 shows an example of SCI operation for multiprocessor format reception.
Section 12 Serial Communication Interface (SCI) 12.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
Section 12 Serial Communication Interface (SCI) Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9.
Section 12 Serial Communication Interface (SCI) Data Transfer Operations SCI initialization (synchronous mode): Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized.
Section 12 Serial Communication Interface (SCI) Serial data transmission (synchronous mode): Figure 12.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 12 Serial Communication Interface (SCI) Figure 12.17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 12.17 Example of SCI Transmit Operation Serial data reception (synchronous mode): Figure 12.
Section 12 Serial Communication Interface (SCI) Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start of reception [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1.
Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
Section 12 Serial Communication Interface (SCI) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start of transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 12 Serial Communication Interface (SCI) 12.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 12.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR.
Section 12 Serial Communication Interface (SCI) A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 12.
Section 12 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
Section 12 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. M = | (0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F – | D – 0.5 | N (1 + F) | × 100% ...
Section 12 Serial Communication Interface (SCI) Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 12.22) • When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI).
Section 12 Serial Communication Interface (SCI) • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception.
Section 12 Serial Communication Interface (SCI) Transition to software standby End of transmission Start of transmission Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Port Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 12.
Section 12 Serial Communication Interface (SCI) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? No Yes Initialization RE = 1 Figure 12.26 Sample Flowchart for Mode Transition during Reception Rev.7.00 Feb.
Section 12 Serial Communication Interface (SCI) Rev.7.00 Feb.
Section 13 Smart Card Interface Section 13 Smart Card Interface 13.1 Overview The SCI supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (identification card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 13.1.1 Features Features of the smart card interface supported by the chip is as follows.
Section 13 Smart Card Interface 13.1.2 Block Diagram Bus interface Figure 13.1 shows a block diagram of the smart card interface.
Section 13 Smart Card Interface 13.1.3 Pin Configuration Table 13.1 shows the smart card interface pin configuration. Table 13.
Section 13 Smart Card Interface 13.1.4 Register Configuration Table 13.2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 12, Serial Communication Interface (SCI). Table 13.
Section 13 Smart Card Interface 13.2 Register Descriptions Registers added with the smart card interface and bits for which the function changes are described here. 13.2.1 Bit Smart Card Mode Register (SCMR) : 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 R/W — — — — R/W R/W — R/W : SCMR is an 8-bit readable/writable register that selects the smart card interface function. SCMR is initialized to H'F2 by a reset and in hardware standby mode.
Section 13 Smart Card Interface Bit 2 SINV Description 0 TDR contents are transmitted as they are (Initial value) Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function.
Section 13 Smart Card Interface Bit 4 ERS Description 0 Indicates data received normally with no error signal [Clearing conditions] 1 (Initial value) • Upon reset, and in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 Indicates an error signal was sent showing detection of a parity error at the receiving side [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its
Section 13 Smart Card Interface 13.2.3 Serial Mode Register (SMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 GM BLK PE* O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: * When the smart card interface is used, set a value of 1 in bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
Section 13 Smart Card Interface Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK Description 0 Normal smart card interface mode operation 1 (Initial value) • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.
Section 13 Smart Card Interface 13.2.4 Bit Serial Control Register (SCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 12.2.6, Serial Control Register (SCR).
Section 13 Smart Card Interface 13.3 Operation 13.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.
Section 13 Smart Card Interface 13.3.2 Pin Connections Figure 13.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data communication line, the chip’s TxD pin and RxD pin should both be connected to the line, as shown in the figure. The data communication line should be pulled up to the VCC power supply with a resistor.
Section 13 Smart Card Interface 13.3.3 Data Format Normal Transfer Mode: Figure 13.3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
Section 13 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor.
Section 13 Smart Card Interface 13.3.4 Register Settings Table 13.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 13.
Section 13 Smart Card Interface Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
Section 13 Smart Card Interface 13.3.5 Clock Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, the clock is output from the SCK pin.
Section 13 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 2n+1 × 106 – 1 ×B Table 13.6 Examples of BRR Settings for Bit Rate B (bits/s) (When n = 0 and S = 372) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.
Section 13 Smart Card Interface 13.3.6 Data Transfer Operations Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR.
Section 13 Smart Card Interface Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 13.4 shows a flowchart for transmitting, and figure 13.5 shows the relation between a transmit operation and the internal registers. [1] Perform smart card interface mode initialization as described above in Initialization.
Section 13 Smart Card Interface Start Initialization Start of transmission ERS = 0? No Yes Error handling No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit to 0 End Figure 13.4 Sample Transmission Flowchart Rev.7.00 Feb.
Section 13 Smart Card Interface TDR (1) Data write Data 1 (2) Transfer from TDR to TSR Data 1 (3) Serial data output Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmissi
Section 13 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 13.7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Section 13 Smart Card Interface With the above processing, interrupt handling or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated.
Section 13 Smart Card Interface Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 13.8 Timing for Fixing Clock Output Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode.
Section 13 Smart Card Interface Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out.
Section 13 Smart Card Interface 13.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode.
Section 13 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 13.3.
Section 13 Smart Card Interface 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.10 Receive Data Sampling Timing in Smart Card Mode (When Using 372-Times Clock) Thus the receive margin in asynchronous mode is given by the following formula. M =⎥ (0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F – ⎥ D – 0.
Section 13 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
Section 13 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 13.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
Section 13 Smart Card Interface Rev.7.00 Feb.
Section 14 A/D Converter (8 Analog Input Channel Version) Section 14 A/D Converter (8 Analog Input Channel Version) 14.1 Overview The chip incorporates a successive-approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected. 14.1.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.1.3 Pin Configuration Table 14.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 14.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.1.4 Register Configuration Table 14.2 summarizes the registers of the A/D converter. Table 14.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.2 Register Descriptions 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.2.2 A/D Control/Status Register (ADCSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation.
Section 14 A/D Converter (8 Analog Input Channel Version) Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 A/D conversion stopped 1 • Single mode A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends • Scan mode A/D conversion is started.
Section 14 A/D Converter (8 Analog Input Channel Version) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits are used together with the SCAN bit to select the analog input channels. Only set the input channel(s) while conversion is stopped (ADST = 0). Group Selection Channel Selection Description CH2 CH1 CH0 0 0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 1 0 1 14.2.
Section 14 A/D Converter (8 Analog Input Channel Version) Bit 7 TRGS1 Bit 6 TRGS0 Description 0 0 A/D conversion start by external trigger is disabled 1 A/D conversion start by external trigger (TPU) is enabled 0 A/D conversion start by external trigger (8-bit timer) is enabled 1 A/D conversion start by external trigger pin (ADTRG) is enabled 1 (Initial value) Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input.
Section 14 A/D Converter (8 Analog Input Channel Version) Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
Section 14 A/D Converter (8 Analog Input Channel Version) Continuous A/D conversion Clear*1 Set*1 ADST Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) A/D conversion time Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer A/D conversion result 1 ADDRA ADDRB A/D conversion result 4 A/D conversion result 2 ADDRC A/D conversion result
Section 14 A/D Converter (8 Analog Input Channel Version) 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing. Table 14.4 indicates the A/D conversion time. As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time.
Section 14 A/D Converter (8 Analog Input Channel Version) Table 14.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS = 0 CKS1 = 1 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay tD 18 — 4 — 5 10 — 17 6 — 9 Input sampling time tSPL — 127 — — 15 — — 63 — — 31 — A/D conversion time tCONV 515 — 67 — 68 259 — 266 131 — 33 530 134 Note: Values in the table are the number of states. Table 14.
Section 14 A/D Converter (8 Analog Input Channel Version) φ ADTRG Internal trigger signal ADST A/D conversion Figure 14.6 External Trigger Input Timing 14.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt.
Section 14 A/D Converter (8 Analog Input Channel Version) 14.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. 2. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS.
Section 14 A/D Converter (8 Analog Input Channel Version) frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref 100 Ω Rin*2 *1 AN0 to AN7 *1 0.1 μF Notes: AVSS Values are reference values. 1. 10 μF 0.01 μF 2 .
Section 14 A/D Converter (8 Analog Input Channel Version) A/D Conversion Precision Definitions: The chip’s A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes. • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 to B'0000000001 (see figure 14.9).
Section 14 A/D Converter (8 Analog Input Channel Version) Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 14.8 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 14.9 A/D Conversion Precision Definitions (2) Rev.7.
Section 14 A/D Converter (8 Analog Input Channel Version) Permissible Signal Source Impedance: The chip’s analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 15 D/A Converter Section 15 D/A Converter 15.1 Overview The chip includes an 8-bit resolution D/A converter with two analog signal output channels. 15.1.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 μs (with 20-pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode • Module stop mode can be set ⎯ As the initial setting, D/A converter operation is halted.
Section 15 D/A Converter 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the D/A converter. Module data bus Vref D/A DA0 converter DACR DA1 DADR1 8-bit DADR0 AVCC AVSS Control circuit Legend: DACR: D/A control register DADR0, DADR1: D/A data registers 0, 1 Figure 15.1 Block Diagram of D/A Converter Rev.7.00 Feb.
Section 15 D/A Converter 15.1.3 Pin Configuration Table 15.1 summarizes the input and output pins of the D/A converter. Table 15.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AVCC Input Analog power source Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin Vref Input Analog reference voltage 15.1.
Section 15 D/A Converter 15.2 Register Descriptions 15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DADR0, DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 15.2.
Section 15 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 is disabled 1 Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently.
Section 15 D/A Converter 15.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 15 D/A Converter 15.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 15.
Section 15 D/A Converter DADR0 write cycle DADR0 write cycle DACR01 write cycle DACR01 write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 15.2 Example of D/A Converter Operation Rev.7.00 Feb.
Section 16 RAM Section 16 RAM 16.1 Overview The chip has on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR).
Section 16 RAM 16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 16.1 shows the address and initial value of SYSCR. Table 16.1 RAM Register Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address. 16.2 Register Descriptions 16.2.
Section 16 RAM 16.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF* are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits.
Section 16 RAM Rev.7.00 Feb.
Section 17 ROM Section 17 ROM 17.1 Overview This LSI has 512, 384, 256, or 128 kbytes of on-chip flash memory, or 512, 384, 256, 128, or 64 kbytes of on-chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the EAE bit in BCRL.
Section 17 ROM 17.1.2 Register Configuration The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROMrelated registers are shown in table 17.1. Table 17.1 ROM Registers Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined H'FF3B Bus controller register BCRL R/W Undefined H'FED5 Note: * Lower 16 bits of the address. 17.2 Register Descriptions 17.2.
Section 17 ROM 17.2.2 Bit Bus Control Register L (BCRL) : Initial value : R/W : 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — — — — WAITE 0 0 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL).
Section 17 ROM Table 17.
Section 17 ROM Notes: 1. Note that in modes 6, 7, 14, and 15, the on-chip ROM that can be used after a reset is the 64-kbyte area from H'000000 to H'00FFFF. 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4.
Section 17 ROM Table 17.
Section 17 ROM 17.4 Overview of Flash Memory (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) 17.4.1 Features The H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT have 384, 256, 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time.
Section 17 ROM • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Note: * Flash memory emulation by RAM is not supported in the H8S/2314 F-ZTAT. 17.4.
Section 17 ROM 17.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a resetstart is executed, the chip enters one of the operating modes shown in figure 17.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
Section 17 ROM 17.4.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 17 ROM • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 17 ROM 17.4.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 17.
Section 17 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 17 ROM 17.4.7 Block Configuration On-chip 128-kbyte flash memory is divided into one 64-kbyte block, one 32-kbyte block, and eight 4-kbyte blocks. On-chip 256-kbyte flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. On-chip 384-kbyte flash memory is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks.
Section 17 ROM 17.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 17.5. Table 17.
Section 17 ROM 17.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17.6. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 17.
Section 17 ROM 17.5 Register Descriptions 17.5.1 Flash Memory Control Register 1 (FLMCR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P 1/0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit.
Section 17 ROM Bit 6 SWE Description 0 Writes disabled 1 Writes enabled (Initial value) [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode.
Section 17 ROM Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.
Section 17 ROM 17.5.2 Bit Flash Memory Control Register 2 (FLMCR2) : 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W R — — — — — — — : FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Section 17 ROM 17.5.3 Bit Erase Block Register 1 (EBR1) : EBR1 Initial value : R/W : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block.
Section 17 ROM Table 17.
Section 17 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Section 17 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Section 17 ROM 17.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17.9. For a diagram of the transitions to the various flash memory modes, see figure 17.3. Table 17.
Section 17 ROM 17.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or H8S/2314 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
Section 17 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data by
Section 17 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or H8S/2314 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
Section 17 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 17.12. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.
Section 17 ROM H'FFDC00 Boot program area (2 kbytes)*2 H'FFE3FF Reserved area used only in boot mode (4 kbytes)*1 H'FFEBFF H'FFEC00 Programming control program area (6 kbytes) H'FFFBFF Notes: 1. This is a reserved area used only in boot mode. It should not be used for any purpose other than flash memory programming/erasing. 2. This area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM.
Section 17 ROM The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 17.
Section 17 ROM The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 17.14 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.
Section 17 ROM 17.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for the on-chip ROM area by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
Section 17 ROM Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) μs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of (y) μs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time.
Section 17 ROM Write pulse application subroutine Start of programming Sub-routine write pulse Start Enable WDT Set SWE bit in FLMCR1 Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 17 ROM 17.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17.16. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 20.3.6, Flash Memory Characteristics.
Section 17 ROM Start *1 Set SWE bit in FLMCR1 Wait (x) μs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR1 Wait (y) μs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) μs *2 Clear ESU bit in FLMCR1 Wait (β) μs *2 Disable WDT Set EV bit in FLMCR1 *2 Wait (γ) μs Set block start address to verify address H'FF dummy write to verify address Wait (ε) μs *2 Read verify data Increment address Verify data = all 1? *3 NG OK NG L
Section 17 ROM 17.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 17.11). Table 17.
Section 17 ROM Table 17.12 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory.) Block specification protection • — Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). • Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state.
Section 17 ROM • When a bus master other than the CPU (the DTC) has control of the bus during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 17.17 shows the flash memory state transition diagram.
Section 17 ROM 17.9 Flash Memory Emulation in RAM 17.9.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 17.
Section 17 ROM 17.9.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 Flash memory EB8 to EB11 (EB8 to EB13)*1 (EB8 and EB9)*2 H'FFEBFF On-chip RAM H'FFFBFF H'3FFFF (H'5FFFF)*1 (H'1FFFF)*2 Notes: 1. H'5FFFF, EB8 to EB13 in the H8S/2315 F-ZTAT. 2.
Section 17 ROM Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2.
Section 17 ROM 17.11 Flash Memory Programmer Mode 17.11.1 Progremmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer* that supports the Renesas Technology microcomputer device type with 256kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Section 17 ROM 17.11.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figure 17.21. This enables the chip to fit a 40-pin socket. Figure 17.20 shows the on-chip ROM memory map and figure 17.21 shows the socket adapter pin assignments. MCU mode address Programmer mode address H'00000000 H'00000 On-chip ROM space 256 kbytes (384 kbytes)*1 (128 kbytes)*2 H'0003FFFF (H'0005FFFF)*1 (H'0001FFFF)*2 H'3FFFF (H'5FFFF)*1 (H'1FFFF)*2 Notes: 1.
Section 17 ROM H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT TFP-100B, FP-100A Pin Name TFP-100G 32 A0 34 Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) Pin No.
Section 17 ROM 17.11.3 Programmer Mode Operation Table 17.14 shows how the different operating modes are set when using programmer mode, and table 17.15 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming.
Section 17 ROM Table 17.14 Settings for Each Operating Mode in Programmer Mode Pin Names Mode FWE CE OE WE I/O7 to I/O0 A18 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z × L H L Data input Ain* H × × Hi-Z × Command write 1 Chip disable* H or L *3 H or L 2 Legend: H: High level L: Low level Hi-Z: High impedance ×: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2.
Section 17 ROM 17.11.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Table 17.
Section 17 ROM Table 17.17 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM Table 17.18 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 μs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 17.
Section 17 ROM 17.11.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
Section 17 ROM AC Characteristics Table 17.19 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM FWE tpnh Address stable A18 to A0 tpns tces tceh tnxtc tnxtc CE OE tf twep tas tr WE tah twsts tspa Data transfer 1 byte to 128 bytes tds tdh twrite I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'40 I/O5 to I/O0 H'00 Figure 17.26 Auto-Program Mode Timing Waveforms 17.11.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing.
Section 17 ROM AC Characteristics Table 17.20 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM 17.11.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 17.21 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM Table 17.
Section 17 ROM 17.11.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the progremmer mode setup period. After the progremmer mode setup time, a transition is made to memory read mode. Table 17.
Section 17 ROM 17.11.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology.
Section 17 ROM FWE application/disconnection (see figures 17.30 to 17.32): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range.
Section 17 ROM However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming.
Section 17 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC tMDS*3 FWE Min 0 μs MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Section 17 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Section 17 ROM φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE bit SWE set Mode change*1 SWE cleared Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohib
Section 17 ROM 17.13 Overview of Flash Memory (H8S/2319 F-ZTAT) 17.13.1 Features The H8S/2319 F-ZTAT has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 17 ROM • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 17.13.
Section 17 ROM 17.13.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 17.34. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
Section 17 ROM 17.13.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 17 ROM • User program mode 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM.
Section 17 ROM 17.13.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 17.
Section 17 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 17 ROM 17.13.7 Block Configuration The flash memory is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'000000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes 512 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'07FFFF Figure 17.39 Flash Memory Block Configuration Rev.7.00 Feb.
Section 17 ROM 17.13.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 17.26. Table 17.
Section 17 ROM 17.13.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17.27. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 17.
Section 17 ROM 17.14 Register Descriptions 17.14.1 Flash Memory Control Register 1 (FLMCR1) Bit : 7 6 5 4 3 2 1 0 FWE1 SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value : 1 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 then setting the EV1 or PV1 bit.
Section 17 ROM Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When SWE1 = 1 Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time.
Section 17 ROM Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When SWE1 = 1 Bit 1—Erase 1 (E1): Selects erase mode transition or clearing for addresses H'000000 to H'03FFFF.
Section 17 ROM 17.14.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 6 5 4 3 2 1 0 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2 Initial value : 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 then setting the EV2 or PV2 bit.
Section 17 ROM Bit 6 SWE2 Description 0 Writes disabled 1 Writes enabled (Initial value) Bit 5—Erase Setup Bit 2 (ESU2): Prepares for a transition to erase mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, PSU2, EV2, PV2, E2, or P2 bit at the same time. Bit 5 ESU2 Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When SWE2 = 1 Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode for addresses H'040000 to H'07FFFF.
Section 17 ROM Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, EV2, E2, or P2 bit at the same time. Bit 2 PV2 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When SWE2 = 1 Bit 1—Erase 2 (E2): Selects erase mode transition or clearing for addresses H'040000 to H'07FFFF.
Section 17 ROM 17.14.3 Erase Block Register 1 (EBR1) Bit : EBR1 Initial value : R/W : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased.
Section 17 ROM 17.14.4 Erase Block Register 2 (EBR2) Bit : EBR2 Initial value : R/W : 7 6 5 4 3 2 1 0 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the SWE1 bit in FLMCR1 is not set.
Section 17 ROM 17.14.5 System Control Register 2 (SYSCR2) Bit : 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W — — R/W : SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified.
Section 17 ROM standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 17.29. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed.
Section 17 ROM 17.15 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17.30. For a diagram of the transitions to the various flash memory modes, see figure 17.34. Table 17.
Section 17 ROM 17.15.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2319 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
Section 17 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data by
Section 17 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2319 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Section 17 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 17.43. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.
Section 17 ROM • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
Section 17 ROM While the SWE1 bit is set to 1 to perform programming or erasing for the addresses H'000000 to H'03FFFF, this address area cannot be read. While the SWE2 bit is set to 1 to perform programming or erasing for the addresses H'040000 to H'07FFFF, this address area cannot be read. The control program that performs programming and erasing should be run in on-chip RAM or flash memory except for the above address areas.
Section 17 ROM 17.16 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Section 17 ROM data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. The 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Section 17 ROM Start of programming Write pulse application subroutine Sub-routine write pulse Start Enable WDT Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU1 (2) bit in FLMCR1 (2) Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 17 ROM 17.16.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for addresses H'040000 to H'07FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17.46. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 20.3.
Section 17 ROM 17.16.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for addresses H'040000 to H'07FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
Section 17 ROM Start *1 Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait (y) μs *2 Start of erase Set E1 (2) bit in FLMCR1 (2) Wait (z) ms *2 Clear E1 (2) bit in FLMCR1(2) n←n+1 Halt erase Wait (α) μs *2 Clear ESU1 (2) bit in FLMCR1 (2) Wait (β) μs *2 Disable WDT Set EV1 (2) bit in FLMCR1 (2) *2 Wait (γ) μs Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) μs *2 Re
Section 17 ROM 17.17 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.17.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 17.32). Table 17.
Section 17 ROM 17.17.2 Software Protection Software protection can be implemented by setting the SWE1 bit in flash memory control register 1 (FLMCR1), SWE2 bit in FLMCR2 erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in FLMCR1, or the P2 or E2 bit in FLMCR2 does not cause a transition to program mode or erase mode (see table 17.33). Table 17.
Section 17 ROM 17.17.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Section 17 ROM Normal operating mode Program mode Erase mode Reset or hardware standby (hardware protection) RES = 0 or STBY = 0 RD VF PR ER FLER = 0 Error occurrence (software standby) RD VF PR ER FLER = 0 RES = 0 or STBY = 0 Error occurrence RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit
Section 17 ROM 17.18 Flash Memory Emulation in RAM 17.18.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 17.
Section 17 ROM 17.18.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'000000 EB0 H'001000 EB1 H'002000 EB2 H'030000 EB3 H'004000 EB4 H'005000 EB5 H'006000 EB6 H'007000 EB7 H'008000 H'FFDC00 H'FFEBFF Flash memory EB8 to EB15 On-chip RAM H'FFFBFF H'07FFFF Figure 17.49 Example of RAM Overlap Operation Example in Which Flash Memory Block Area EB1 Is Overlapped 1.
Section 17 ROM the P2 or E2 bit in FLMCR2 will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 17.
Section 17 ROM 17.20 Flash Memory Programmer Mode 17.20.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 512kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Section 17 ROM 17.20.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figure 17.51. This enables the chip to fit a 40-pin socket. Figure 17.50 shows the on-chip ROM memory map and figure 17.51 shows the socket adapter pin assignments. MCU mode address Programmer mode address H'00000 H'00000000 On-chip ROM space (512 kbytes) H'0007FFFF H'7FFFF Figure 17.50 Memory Map in Programmer Mode Rev.7.00 Feb.
Section 17 ROM H8S/2319 F-ZTAT Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) TFP-100B FP-100A Pin Name Pin No.
Section 17 ROM 17.20.3 Programmer Mode Operation Table 17.35 shows how the different operating modes are set when using programmer mode, and table 17.36 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming.
Section 17 ROM Table 17.36 Programmer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write × H'00 Read RA Dout Auto-program mode 129 Write × H'40 Write PA Din Auto-erase mode 2 Write × H'20 Write × H'20 Status read mode 2 Write × H'71 Write × H'71 Legend: RA: Read address PA: Program address ×: Don’t care Notes: 1.
Section 17 ROM Table 17.37 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM Table 17.38 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM Table 17.39 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 μs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 17.
Section 17 ROM 17.20.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
Section 17 ROM AC Characteristics Table 17.40 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 17 ROM 17.20.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write.
Section 17 ROM A18 to A0 tnxtc tceh tnxtc tces CE OE WE twep tf tds tspa tests tr terase tdh I/O7 Erase end identification signal I/O6 Erase normal end confirmation signal H'20 I/O5 to I/O0 H'00 H'20 Figure 17.57 Auto-Erase Mode Timing Waveforms 17.20.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Section 17 ROM A18 to A0 tceh tnxtc tces tces tceh tnxtc tnxtc CE tce OE WE tf twep tr tf tdh tds twep tds H'71 I/O7 to I/O0 toe tr tdf tdh H'71 Note: I/O3 and I/O2 are undefined. Figure 17.58 Status Read Mode Timing Waveforms Table 17.
Section 17 ROM Table 17.44 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 17.20.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 17.
Section 17 ROM • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2.
Section 17 ROM 17.21 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
Section 17 ROM Do not use interrupts while flash memory is being programmed or erased: When flash memory is programmed or erased, all interrupt requests, including NMI, should be disabled to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block.
Section 17 ROM 17.22 Overview of Flash Memory (H8S/2319C 0.18µm F-ZTAT) 17.22.1 Features This LSI has an on-chip 512-kbyte flash memory. The flash memory has the following features. • Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting in the initiation determines which memory MAT is initiated first.
Section 17 ROM When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. • Programming/erasing time The flash memory programming time is 3 ms (typ) for 128-byte simultaneous programming, which is equivalent to 25 µs per byte. The erasing time is 1000 ms (typ) per 64-kbyte block. • Number of programming Flash memory programming can be performed a minimum of 100 times. Rev.7.00 Feb.
Section 17 ROM 17.22.
Section 17 ROM 17.22.3 Operating Mode of Flash Memory When each mode pin is set in the reset state and reset start is performed, the microcomputer enters each operating mode as shown in figure 17.61. For the setting of each mode pin, see table 17.52. • Flash memory cannot be read, programmed, or erased in ROM invalid mode. • Flash memory can be read in user mode, but cannot be programmed or erased.
Section 17 ROM 17.22.4 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and PROM mode is shown in table 17.46. Table 17.
Section 17 ROM 17.22.5 Flash MAT Configuration This LSI's flash memory is configured by the 512-kbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and PROM mode.
Section 17 ROM 17.22.6 Block Division The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 17.63. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 kbytes.
Section 17 ROM 17.22.7 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 17.24.2, User Program Mode.
Section 17 ROM 2. Download of on-chip program The on-chip program is automatically downloaded by setting the SCO bit in the flash key code register (FKEY) and the flash code control and status register (FCCS), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading.
Section 17 ROM Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. 17.22.8 Pin Configuration Flash memory is controlled by the pin as shown in table 17.47. Table 17.
Section 17 ROM There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 17.49. Table 17.
Section 17 ROM Table 17.49 Register/Parameter and Target Mode Initialization Programming Erasure Read RAM Emulation FCCS — — — — — FPCS — — — — — PECS — — — — — FKEY — Download Programming/ erasing interface registers FMATS Programming/ erasing interface parameter RAM emulation — — *1 — *1 FPFR — — *2 — — — — — — FPEFEQ — FMPAR — — — — — FMPDR — — — — — FEBS — — — — — RAMER — — — — — Notes: 1.
Section 17 ROM (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the error occurrence during programming or erasing flash memory and the download of on-chip program. Bit : 7 6 5 4 3 2 1 0 — — — FLER — — — SCO Initial value : 1 0 0 0 0 0 0 0 R/W R R R R R R R (R)/W : Bit 7—Reserved: This bit is always read as 1. The write value should always be 1. Bits 6 and 5—Reserved: These bits are always read as 0.
Section 17 ROM Bit 0—Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM.
Section 17 ROM (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit : 7 6 5 4 3 2 1 0 — — — — — — — PPVS Initial value : 0 0 0 0 0 0 0 0 R/W R R R R R R R R/W : Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0. Bit 0—Program Pulse Verify (PPVS): Selects the programming program.
Section 17 ROM (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
Section 17 ROM (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected.
Section 17 ROM (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFBC00) in on-chip RAM.
Section 17 ROM Bits 6 to 0 TDA6 to TDA0 Description H'00 Download start address is set to H'FFBC00 H'01 Download start address is set to H'FFCC00 H'02 Download start address is set to H'FFDC00 H'03 Download start address is set to H'FFEC00 H'04 to H'7F Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. 17.23.
Section 17 ROM Table 17.
Section 17 ROM Bit : 7 6 5 4 3 2 1 0 0 0 0 0 0 SS FK SF Initial value : — — — — — — — — R/W — — — — — R/W R/W R/W : Bits 7 to 3—Reserved: Return 0. Bit 2—Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred.
Section 17 ROM (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings.
Section 17 ROM Bits 15 to 0—Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register ER0). For example, when the operating frequency of the CPU is 25.
Section 17 ROM (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register ER1 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter).
Section 17 ROM (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR.
Section 17 ROM (b) Flash multipurpose data destination parameter (FMPDR: general register ER0 of CPU): This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR.
Section 17 ROM (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the programming result is provided here. Bit : 7 6 5 4 3 2 1 0 0 MD EE FK 0 WD WA SF Initial value : — — — — — — — — R/W — R/W R/W R/W — R/W R/W R/W : Bit 7—Reserved: Returns 0. Bit 6—Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the error protection state has been entered.
Section 17 ROM Bit 4—Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'5A) 1 FKEY setting is error (FKEY = value other than H'5A) Bit 3—Reserved: Returns 0. Bit 2—Write Data Address Detect (WD): When flash memory area is specified as the start address of the storage destination of the program data, an error occurs.
Section 17 ROM (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 17.24.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number.
Section 17 ROM (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the erase result is provided here. Bit : 7 6 5 4 3 2 1 0 0 MD EE FK EB 0 0 SF Initial value : — — — — — — — — R/W — R/W R/W R/W R/W — — R/W : Bit 7—Reserved: Returns 0. Bit 6—Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the error protection state has been entered.
Section 17 ROM Bit 4—Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'5A) 1 FKEY setting is error (FKEY = value other than H'5A) Bit 3—Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT.
Section 17 ROM 17.23.3 System Control Register 2 (SYSCR2) Bit : 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W — — R/W : SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified.
Section 17 ROM 17.23.4 RAM Emulation Register (RAMER) Bit : 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W R/W R/W R/W : RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode.
Section 17 ROM Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (see table 17.51). Table 17.
Section 17 ROM 17.24 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. Table 17.52 lists the pin setting for entering each mode. For details on the state transition of each mode for flash memory, see figure 17.61. Table 17.
Section 17 ROM This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 17.65 System Configuration in Boot Mode SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
Section 17 ROM Table 17.53 System Clock Frequency that can Automatically Adjust Bit Rate of This LSI Bit rate of host System Clock Frequency Which Can Automatically Adjust Bit Rate of This LSI 19,200 bps 16 MHz to 25 MHz 9,600 bps 8 MHz to 25 MHz State Transition: The overview of the state transition after boot mode is initiated is shown in figure 17.67. For details on boot mode, refer to section 17.29.1, Serial Communications Interface Specification for Boot Mode.
Section 17 ROM Note that memory read of the user MAT/user boot MAT can only read the program data after all user MAT/user boot MAT has automatically been erased.
Section 17 ROM 17.24.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The programming/erasing overview flow is shown in figure 17.68. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed. Doing so may cause damage or destroy flash memory.
Section 17 ROM On-Chip RAM Address Map when Programming/Erasing Is Executed: Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and judgement of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 17.69 shows the program area to be downloaded.
Section 17 ROM Programming Procedure in User Program Mode: The procedures for download, initialization, and programming are shown in figure 17.70.
Section 17 ROM When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shorted. [1] Select the on-chip program to be downloaded and the download destination. When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time.
Section 17 ROM • No interrupts are accepted during download processing. However, interrupt requests are held, so when processing returns to the user procedure program and interrupts are generated. When the level-detection interrupt requests are to be held, interrupts must be put until the download is ended. • When hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
Section 17 ROM [7] Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.
Section 17 ROM [11] The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1. The start address of the program data storage area (FMPDR) is set to general register ER0. • Example of the FMPAR setting FMPAR specifies the programming destination address.
Section 17 ROM [15] After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 μs. Erasing Procedure in User Program Mode: The procedures for download, initialization, and erasing are shown in figure 17.71.
Section 17 ROM A single divided block is erased by one erasing processing. For block divisions, refer to figure 17.63, Block Division of User MAT. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. [1] Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time.
Section 17 ROM [6] After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasure has finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 μs. Erasing and Programming Procedure in User Program Mode: By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 17.
Section 17 ROM Download and initialization are performed only once at the beginning. In this kind of operation, note the following: • Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas.
Section 17 ROM 1 Start programming procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT Yes No Download error processing Set the FPEFEQ and parameter Initialization JSR FTDAR setting+32 FPFR=0 ? Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 Programming Clear FKEY to 0 User-MAT selection state Download Set FKEY to H'5A Set SCO to 1 and execute download DPFR=0 ? I
Section 17 ROM vector is read from is undetermined. Perform MAT switching in accordance with the description in section 17.27, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.29.3, Procedure Program and Storable Area for Programming Data.
Section 17 ROM The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 17.74. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined.
Section 17 ROM 17.25 Protection There are three kinds of flash memory program/erase protection: hardware, software protection, and error protection. 17.25.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible.
Section 17 ROM 17.25.2 Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM-emulation register. Table 17.55 Software Protection Function to Be Protected Item Description Protection by the SCO bit • Clearing the SCO bit in the FCCS register makes the device enter a program/erase-protected state, and this disables the downloading of the programming/erasing programs.
Section 17 ROM (1) When an interrupt, such as NMI, has occurred during programming/erasing (2) When the relevant block area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) (3) When a SLEEP instruction (including software standby mode) is executed during programming/erasing (4) When a bus master other than the CPU, such as DTC or BREQ, has obtained the bus right during programming/erasing Error protection is cancelled only by a power-on reset or by hardwa
Section 17 ROM 17.26 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER). After the RAMER setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in both user mode and user-program mode. Figure 17.
Section 17 ROM This area is accessible as both a RAM area and as a flash memory area. H'00000 EB0 H'01000 EB1 H'02000 H'03000 H'04000 EB2 EB3 EB4 H'05000 EB5 H'06000 EB6 H'07000 H'FFBC00 EB7 H'FFDC00 H'FFEBFF H'08000 Flash memory (user MAT) On-chip RAM EB8 to EB15 H'7FFFF H'FFFBFF Figure 17.77 Example of a RAM-Overlap Operation Figure 17.77 shows an example of an overlap on block area EB0 of the flash memory.
Section 17 ROM Figure 17.78 shows an example of programming of the data, after emulation has been completed, to the EB0 area in the user MAT. H'00000 H'01000 H'02000 EB0 EB1 EB2 H'03000 EB3 H'04000 EB4 H'05000 H'06000 H'07000 [1] Cancel the emulation mode. [2] Transfer the user-created program/ erase-procedure program. [3] Download the on-chip programming/erasing programs, avoiding the tuning data area set in FTDAR. [4] Execute programming after erasing, as necessary.
Section 17 ROM 17.27 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or PROM mode.) (1) MAT switching by the FMATS register should always be executed from the on-chip RAM.
Section 17 ROM Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT [1] Mask interrupts [2] Write H'AA to the FMATS register. [3] Execute 4 NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT [1] Mask interrupts [2] Write a value other than H'AA to the FMATS register. [3] Execute 4 NOP instructions before or after accessing the user MAT.
Section 17 ROM 4. Monitoring runaway by WDT Unlike the conventional F-ZTAT H8S microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. 17.
Section 17 ROM 17.28.1 Pin Arrangement of the Socket Adapter Attach the socket adapter to the LSI in the way shown in figure 17.81. This allows conversion to 40 pins. Figure 17.80 shows the memory mapping of the on-chip ROM, and figure 17.81 shows the arrangement of the socket adapter's pins.
Section 17 ROM HN27C4096HG (40 pins) H8S/2319 C F-ZTAT TLP-113V FP-100A Socket Adapter (40-Pin Conversion) Pin No.
Section 17 ROM 17.28.2 PROM Mode Operation Table 17.57 shows the settings for the operating modes of PROM mode, and table 17.58 lists the commands used in PROM mode. The following sections provide detailed information on each mode. • Memory-read mode: This mode supports reading, in units of bytes, from the user MAT or user boot MAT. • Auto-program mode: This mode supports the simultaneous programming of the user MAT and user boot MAT in 128-byte units.
Section 17 ROM Table 17.
Section 17 ROM 17.28.4 Auto-Program Mode (1) In auto-program mode, programming is in 128-byte units. That is, 128 bytes of data are transferred in succession. (2) Even in the programming of less than 128 bytes, 128 bytes of data must be transferred. H'FF should be written to those addresses that are unnecessarily written to. (3) Set the low seven bits of the address to be transferred to low level.
Section 17 ROM 17.28.6 Status-Read Mode (1) Status-read mode is used to determine the type of an abnormal termination. Use this mode when automatic programming or automatic erasure ends abnormally. (2) The return code is retained until writing of a command that selects a mode other than statusread mode. Table 17.59 lists the return codes of status-read mode. For the AC characteristics in status-read mode, see section 17.29.2, AC Characteristics and Timing in PROM Mode. Table 17.
Section 17 ROM 17.28.8 Time Taken in Transition to PROM Mode Until oscillation has stabilized and while PROM mode is being set up, the LSI is unable to accept commands. After the PROM-mode setup time has elapsed, the LSI enters memory-read mode. See section 17.29.2, AC Characteristics and Timing in PROM Mode. 17.28.9 Notes on Using PROM Mode (1) When programming addresses which have previously been programmed, apply auto-erasing before auto-programming.
Section 17 ROM 17.29 Further Information 17.29.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. Status The boot program has three states. (1) Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host.
Section 17 ROM Reset Bit-Rate-Adjustment State Inquiry/Selection wait Transition to Programming/erasing Inquiry Selection Operations for Inquiry Operations for Selection Operations for Erasing User MATs and User Boot MATs Programming/erasing selection wait Programming Operations for Programming Erasing Checking Operations for Erasing Operations for Checking Figure 17.
Section 17 ROM Host Boot Program H'00 (30 times maximum) Measuring the 1-Bit Length H'00 (Completion of Adjustment) H'55 H'E6 (Response to Boot) H'FF (Error) Figure 17.83 Bit-Rate-Adjustment Sequence Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. (1) One-byte commands and one-byte responses These commands and responses are comprised of a single byte.
Section 17 ROM One-Byte Command or One-Byte Response Command or Response n-Byte Command or n-Byte Response Data Size Checksum Command or Response Error Response Error Code Error Response 128-Byte Programming Address Data (n bytes) Checksum Command Memory Read Response Size Data Response Checksum Figure 17.
Section 17 ROM Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 17.
Section 17 ROM All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40).
Section 17 ROM • Device code (4 bytes): Device code returned in response to the supported device inquiry (ASCII-code) • SUM (1 byte): Checksum Response H'06 • Response, H'06, (1 byte): Response to the device selection command ACK will be returned when the device code matches.
Section 17 ROM Response H'06 • Response, H'06, (1 byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR • Error response, H'91, (1 byte): Error response to the clock mode selection command • ERROR, (1 byte) : Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even when the clock mode value is H'00 or H'01 for clock mode inquiry, clock mode selection is performed for each value.
Section 17 ROM ⎯ Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types.
Section 17 ROM (7) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
Section 17 ROM • Area-Last Address (4 bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. • SUM (1 byte): Checksum (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
Section 17 ROM (11) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Section 17 ROM Response H'06 • Response, H'06, (1 byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error Response H'BF ERROR • Error response, H'BF, (1 byte): Error response to selection of new bit rate • ERROR: (1 byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range.
Section 17 ROM (3) Operating frequency error Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below.
Section 17 ROM Boot program Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 17.85 New Bit-Rate Selection Sequence Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order.
Section 17 ROM Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples.
Section 17 ROM Table 17.
Section 17 ROM Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for programming-selection and 128-byte programming commands is shown in figure 17.86.
Section 17 ROM (3) User MAT Programming Selection. The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Command H'43 • Command, H'43, (1 byte): User-program programming selection Response H'06 • Response, H'06, (1 byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK.
Section 17 ROM Error Response H'D0 ERROR • Error response, H'D0, (1 byte): Error response for 128-byte programming • ERROR: (1 byte): Error code H'11: Checksum error H'2A: Address error The address is not within the specified range. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80.
Section 17 ROM Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing.
Section 17 ROM Error Response H'C8 ERROR • Error response: H'C8 (1 byte): Error response to erasing selection • ERROR: (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block Number SUM • Command, H'58, (1 byte): Erasure • Size (1 byte): The number of bytes that represents the erasure block number This is fixed to 1.
Section 17 ROM • Block Number (1 byte): H'FF Stop code for erasure • SUM (1 byte): Checksum Response H'06 • Response, H'06, (1 byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Memory Read The boot program will return the data in the specified address.
Section 17 ROM H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program.
Section 17 ROM User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C • Command, H'4C, (1 byte): Blank check for user boot MAT Response H'06 • Response, H'06, (1 byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK.
Section 17 ROM Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (1 byte): Inquiry regarding boot program's state Response H'5F Size STATUS ERROR SUM • Response, H'5F, (1 byte): Response to boot program state inquiry • Size (1 byte): The number of bytes that represents the STATUS and ERROR. This is fixed to 2.
Section 17 ROM Table 17.63 Status Code Code Description H'11 Device Selection Wait H'12 Clock Mode Selection Wait H'13 Bit Rate Selection Wait H'IF Programming/Erasing State Transition Wait (Bit rate selection is completed) H'31 Programming State for Erasure H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F Programming Data Receive Wait (Programming is completed) H'5F Erasure Block Specification Wait (Erasure is completed) Table 17.
Section 17 ROM 17.29.2 AC Characteristics and Timing in PROM Mode Table 17.65 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V ± 0.
Section 17 ROM Table 17.66 AC Characteristics in Transition from Memory Read Mode to Others Condition: VCC = 3.3 V ± 0.
Section 17 ROM Table 17.67 AC Characteristics Memory Read Mode Condition: VCC = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 25˚C ± 5˚C Code Symbol Min Max Unit Access time tacc — 20 μs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns Address Stable A18-0 CE VIL OE VIL WE VIH Address Stable tacc tacc toh toh I/O7-0 Figure 17.
Section 17 ROM Table 17.68 AC Characteristics Auto-PROM Mode Condition: VCC = 3.3 V ± 0.
Section 17 ROM Table 17.69 AC Characteristics Auto-Erase Mode Condition: VCC = 3.3 V ± 0.
Section 17 ROM Table 17.70 AC Characteristics Status Read Mode Condition: VCC = 3.3 V ± 0.
Section 17 ROM tosc1 tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification t dwn VCC RES Command acceptance Figure 17.95 Oscillation Stabilization Time, PROM Mode Setup Time, and Power-Down Sequence 17.29.3 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM.
Section 17 ROM Transitions to the reset state, and hardware standby mode are inhibited during programming/erasing. When the reset signal is accidentally input to the chip, a longer period in the reset state than usual (100 μs) is needed before the reset signal is released. (7) Switching of the MATs by FMATS should be needed when programming/erasing of the user boot MAT is operated in user-boot mode. The program which switches the MATs should be executed from the on-chip RAM. See section 17.
Section 17 ROM Table 17.
Section 17 ROM Table 17.
Section 17 ROM Table 17.
Section 17 ROM Table 17.
Section 18 Clock Pulse Generator Section 18 Clock Pulse Generator 18.1 Overview The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit.
Section 18 Clock Pulse Generator 18.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 18.1 shows the register configuration. Table 18.1 Clock Pulse Generator Register Name Abbreviation R/W Initial Value Address* System clock control register SCKCR R/W H'00 H'FF3A Note: * Lower 16 bits of the address. 18.2 Register Descriptions 18.2.
Section 18 Clock Pulse Generator Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the division ratio. As the frequency of φ changes, the following points must be noted.
Section 18 Clock Pulse Generator Bit 2 SCK2 Bit 1 SCK1 Bit 0 SCK0 0 0 1 1 0 1 18.
Section 18 Clock Pulse Generator Crystal Resonator: Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.3 and the same resonance frequency as the system clock (φ). CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 18.3 Crystal Resonator Equivalent Circuit Table 18.
Section 18 Clock Pulse Generator 18.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 18.
Section 18 Clock Pulse Generator External Clock: The external clock signal should have the same frequency as the system clock (φ). Table 18.4 and figure 18.6 show the input conditions for the external clock. Table 18.4 External Clock Input Conditions VCC = 2.7 V to 3.3 V VCC = 3.0 V to 3.6 V Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 20 — 10 — ns Figure 18.
Section 18 Clock Pulse Generator 18.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 18.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 18.
Section 19 Power-Down Modes Section 19 Power-Down Modes 19.1 Overview In addition to the normal program execution state, the chip has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The chip operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Sleep mode 4. Module stop mode 5. Software standby mode 6.
Section 19 Power-Down Modes Table 19.
Section 19 Power-Down Modes 19.2 Register Descriptions 19.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — IRQ37S 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — R/W SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Section 19 Power-Down Modes Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states* 1 1 0 1 (Initial value) Note: * Not available in the F-ZTAT versions.
Section 19 Power-Down Modes 19.2.
Section 19 Power-Down Modes • The division ratio can be changed while the chip is operating. The clock output from the φ pin will also change when the division ratio is changed. The frequency of the clock output from the φ pin in this case will be as follows: φ = EXTAL × n Where: EXTAL: Crystal resonator or external clock frequency Division ratio (n = φ/2, φ/4, or φ/8) n: • Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits SCK2 to SCK0.
Section 19 Power-Down Modes 19.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Section 19 Power-Down Modes If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
Section 19 Power-Down Modes 19.5 Module Stop Mode 19.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 19.3 shows MSTP bits and the corresponding on-chip supporting modules.
Section 19 Power-Down Modes Table 19.
Section 19 Power-Down Modes 19.6 Software Standby Mode 19.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.
Section 19 Power-Down Modes 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 19.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 19.
Section 19 Power-Down Modes Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 19.2 Software Standby Mode Application Example 19.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained.
Section 19 Power-Down Modes 19.7 Hardware Standby Mode 19.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
Section 19 Power-Down Modes Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 19.3 Hardware Standby Mode Timing 19.8 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0.
Section 19 Power-Down Modes Rev.7.00 Feb.
Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Electrical Characteristics of Mask ROM Version (H8S/2319, H8S/2318, H8S/2317S, H8S/2316S, H8S/2315, H8S/2314) and ROMless Version (H8S/2312S) 20.1.1 Absolute Maximum Ratings Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.3 V Input voltage (except port 4) Vin –0.3 to VCC +0.3 V Input voltage (port 4) Vin –0.
Section 20 Electrical Characteristics 20.1.2 DC Characteristics Table 20.2 DC Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage VT Input high voltage RES, STBY, NMI, MD2 to MD0 Min Typ Max – VCC × 0.2 — — V + — — VCC × 0.7 V — V VT VT – VT VCC × 0.
Section 20 Electrical Characteristics Item Symbol Min Typ Max Unit Test Conditions Input pull-up Ports A to E MOS current –Ip 10 — 300 μA Vin = 0V Input RES capacitance NMI Cin — — 30 pF Vin = 0 V — — 30 pF f = 1 MHz — — 15 pF Ta = 25°C All input pins except RES and NMI Current Normal operation 2 dissipation* 4 ICC* Sleep mode Standby mode 35 (3.0 V) 80 mA f = 20 MHz 50 (3.3 V) 100 mA f = 25 MHz 25 (3.0 V) 64 mA f = 20 MHz 35 (3.3 V) 80 mA f = 25 MHz — 0.
Section 20 Electrical Characteristics Table 20.3 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins IOL — — 2.
Section 20 Electrical Characteristics (1) Clock Timing Table 20.4 Clock Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics tcyc tCH tCf φ tCL tCr Figure 20.2 System Clock Timing EXTAL tDEXT tDEXT VCC STBY NMI tOSC1 RES φ Figure 20.3 Oscillation Stabilization Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics (2) Control Signal Timing Table 20.5 Control Signal Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics φ tRESS tRESS RES tRESW Figure 20.4 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 20.5 Interrupt Input Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics (3) Bus Timing Table 20.6 Bus Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions WR delay time 1 tWRD1 — 20 — 15 ns Figures 20.6 to 20.10 WR delay time 2 tWRD2 — 20 — 15 ns WR pulse width 1 tWSW1 1.0 × tcyc – 20 — 1.0 × tcyc – 15 — ns WR pulse width 2 tWSW2 1.5 × tcyc – 20 — 1.5 × tcyc – 15 — ns Write data delay time tWDD — 30 — 20 ns Write data setup time tWDS 0.5 × tcyc – 20 — 0.
Section 20 Electrical Characteristics T1 T2 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC2 tRDS tRDH tACC3 tAS tRSD2 D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 20.6 Basic Bus Timing (2-State Access) Rev.7.00 Feb.
Section 20 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC4 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 HWR, LWR (write) tWDD tWDS tWRD2 tWSW2 D15 to D0 (write) Figure 20.7 Basic Bus Timing (3-State Access) Rev.7.00 Feb.
Section 20 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR (write) D15 to D0 (write) WAIT Figure 20.8 Basic Bus Timing (3-State Access, 1 Wait) Rev.7.00 Feb.
Section 20 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) Figure 20.9 Burst ROM Access Timing (2-State Access) Rev.7.00 Feb.
Section 20 Electrical Characteristics T1 T2 or T3 T1 φ tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 20.10 Burst ROM Access Timing (1-State Access) Rev.7.00 Feb.
Section 20 Electrical Characteristics φ tBRQS tBRQS BREQ tBACD tBACD BACK A23 to A0, CS7 to CS0, AS, RD, HWR, LWR tBZD tBZD Figure 20.11 External Bus Release Timing φ tBRQOD tBRQOD BREQO Figure 20.12 External Bus Request Output Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 20.7 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics Condition A Min Max Min Max Unit Test Conditions Asynchronous tScyc 4 — 4 — tcyc Figure 20.20 Synchronous 6 — 6 — Item SCI A/D converter Symbol Input clock cycle Condition B Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 — 1.5 tcyc Input clock fall time tSCKf — 1.5 — 1.
Section 20 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 20.14 TPU Input/Output Timing φ tTCKS TCLKA to TCLKD tTCKWL tTCKS tTCKWH Figure 20.15 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 20.16 8-Bit Timer Output Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 20.17 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 20.18 8-Bit Timer Reset Input Timing φ tWOVD tWOVD WDTOVF Figure 20.19 WDT Output Timing tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 20.20 SCK Clock Input Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 20.21 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 20.22 A/D Converter External Trigger Input Timing Rev.7.00 Feb.
Section 20 Electrical Characteristics 20.1.4 A/D Conversion Characteristics Table 20.8 A/D Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics 20.1.5 D/A Conversion Characteristics Table 20.9 D/A Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics 20.2 Electrical Characteristics of F-ZTAT Versions (H8S/2319 F-ZTAT, H8S/2319E F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) 20.2.1 Absolute Maximum Ratings Table 20.10 Absolute Maximum Ratings Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.11 DC Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage VT Input high voltage Input low voltage RES, STBY, NMI, MD2 to MD0, FWE, EMLE Min Typ Max – VCC × 0.2 — — V + — — VCC × 0.
Section 20 Electrical Characteristics Item Three-state leakage current (off state) Min Typ Max Unit | ITSI | — — 1.0 μA Vin = 0.5 V to VCC – 0.5 V –Ip 10 — 300 μA VCC = 3.0 V to 3.6 V, Vin = 0 V Cin — — 30 pF Vin = 0 V NMI — — 30 pF f = 1 MHz All input pins except RES and NMI — — 15 pF Ta = 25°C — 50 (3.3 V) 100 mA f = 25 MHz 35 (3.3 V) 80 mA — 0.01 10 μA Ta ≤ 50°C — — 80 μA 50°C < Ta — 0.2 (3.0 V) 2.0 mA — 0.01 5.0 μA — 1.4 (3.0 V) 3.
Section 20 Electrical Characteristics Table 20.12 Permissible Output Currents Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins IOL — — 2.
Section 20 Electrical Characteristics 20.2.3 AC Characteristics (1) Clock Timing Table 20.13 Clock Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 500 ns Figure 20.
Section 20 Electrical Characteristics (2) Control Signal Timing Table 20.14 Control Signal Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 20.
Section 20 Electrical Characteristics (3) Bus Timing Table 20.15 Bus Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Figures 20.6 to 20.10 Address setup time tAS 0.5 × tcyc – 15 — ns Address hold time tAH 0.
Section 20 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 20.16 Timing of On-Chip Supporting Modules Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item I/O ports TPU 8-bit timer SCI A/D converter Symbol Min Max Unit Test Conditions Output data delay time tPWD — 40 ns Figure 20.
Section 20 Electrical Characteristics 20.2.4 A/D Conversion Characteristics Table 20.17 A/D Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time 10.
Section 20 Electrical Characteristics 20.2.6 Flash Memory Characteristics Table 20.19 Flash Memory Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (In the H8S/2318, H8S/2317, H8S/2315, and H8S/2314, indicates the total time during which the P bit in flash memory control register 1 (FLMCR1) is set. In the H8S/2319, indicates the total time during which the P1 bit and P2 bit in the flash memory control registers (FLMCR1, FLMCR2) are set. Does not include the program-verify time.) 3.
Section 20 Electrical Characteristics 20.3 Electrical Characteristics of F-ZTAT Version (H8S/2319C F-ZTAT) 20.3.1 Absolute Maximum Ratings Table 20.20 Absolute Maximum Ratings Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol *1 Value Unit –0.3 to +4.3 V Power supply voltage VCC Input voltage (except port 4) Vin –0.3 to VCC +0.
Section 20 Electrical Characteristics 20.3.2 DC Characteristics Table 20.21 DC Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage VT – + VT Min Typ Max Unit VCC × 0.2 — — V — — VCC × 0.7 V — V VT – VT VCC × 0.
Section 20 Electrical Characteristics Test Conditions Item Symbol Min Typ Max Unit Input pull-up Ports A to E MOS current –Ip 10 — 300 μA VCC = 3.0 V to 3.6 V, Vin = 0 V Cin — — 30 pF Vin = 0 V NMI — — 30 pF f = 1 MHz All input pins except RES and NMI — — 15 pF Ta = 25°C — 25 (3.3 V) 50 mA f = 25 MHz 17 (3.3 V) 40 mA — 20 90 μA Ta ≤ 50°C — — 120 μA 50°C < Ta — 1.0 (3.0 V) 2.0 mA — 1.0 5.0 μA — 1.4 (3.0 V) 3.0 mA — 0.2 5.0 μA 2.
Section 20 Electrical Characteristics Table 20.22 Permissible Output Currents Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins IOL — — 2.
Section 20 Electrical Characteristics 20.3.3 AC Characteristics (1) Clock Timing Table 20.23 Clock Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 500 ns Figure 20.
Section 20 Electrical Characteristics (2) Control Signal Timing Table 20.24 Control Signal Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 20.
Section 20 Electrical Characteristics (3) Bus Timing Table 20.25 Bus Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Figures 20.6 to 20.10 Address setup time tAS 0.5 × tcyc – 15 — ns Address hold time tAH 0.
Section 20 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 20.26 Timing of On-Chip Supporting Modules Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item I/O ports TPU 8-bit timer SCI A/D converter Symbol Min Max Unit Test Conditions Output data delay time tPWD — 40 ns Figure 20.
Section 20 Electrical Characteristics 20.3.4 A/D Conversion Characteristics Table 20.27 A/D Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time 10.
Section 20 Electrical Characteristics 20.3.6 Flash Memory Characteristics Table 20.29 Flash Memory Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 20 Electrical Characteristics 20.3.7 Usage Note (Internal voltage step down for the H8S/2319C F-ZTAT) The H8S/2319C F-ZTAT has an on-chip voltage step down circuit that automatically lowers the power supply voltage, inside the microcomputer, to an adequate level. A capacitor (0.1 µF) should be connected between the internal voltage step down circuit pin (VCL pin) and the VSS pin to stabilize the internal voltage. Figure 20.23 shows how to connect the capacitor.
Section 20 Electrical Characteristics Rev.7.00 Feb.
Appendix A Instruction Set Appendix A Instruction Set A.
Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of the instruction * Undetermined (no guaranteed value) 0 Always cleared to 0 1 Always set to 1 — Not affected by execution of the instruction Rev.7.00 Feb.
MOV B B B B B B B MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 W B MOV.B @aa:16,Rd MOV.W @ERs,Rd B MOV.B @aa:8,Rd W B MOV.B @ERs+,Rd MOV.W Rs,Rd B MOV.B @(d:32,ERs),Rd B B MOV.B @(d:16,ERs),Rd W 4 B MOV.B @ERs,Rd MOV.W #xx:16,Rd B MOV.B Rs,@aa:32 B 2 MOV.B Rs,Rd 2 2 Operand Size #xx Rn MOV.
MOV Rev.7.00 Feb. 14, 2007 page 866 of 1108 REJ09B0089-0700 W W W L 6 L L L L MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd L W MOV.W Rs,@(d:16,ERd) MOV.L @aa:32,ERd W MOV.W Rs,@ERd L W MOV.W @aa:32,Rd L W MOV.W @aa:16,Rd MOV.L @aa:16,ERd W MOV.W @ERs+,Rd MOV.L @ERs+,ERd W W MOV.
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) [2] [2] Cannot be used in the chip Cannot be used in the chip MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MOVFPE MOVTPE 4 Repeated for each register saved (SP-4→SP,ERn32→@SP) Repeated for each register restored L STM (ERm-ERn),@-SP ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 7/9/11 [1] 7/9/11 [1] 5 3 STM 4 0 ⎯ 0 ⎯ L 4 2 LDM @SP+,(ERm-ERn) 5 3 6 LDM 0 ⎯ 0 ⎯ 5 L PUSH 4 2 0 ⎯ ⎯ ⎯ ERs32→@aa:32 0
W L 6 L B 2 B L L L B W W L L B B W 4 ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX #xx:8,Rd ADDX Rs,Rd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd DAA SUB INC ADDS ADDX B W 4 ADD.W #xx:16,Rd B 2 ADD.B #xx:8,Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa ADD.
L L B B W B W DEC.L #1,ERd DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS.B Rs,Rd MULXS.W Rs,ERd DAS MULXU MULXS DEC W L SUBS #2,ERd DEC.W #2,Rd L SUBS #1,ERd W B SUBX Rs,Rd DEC.W #1,Rd B 2 SUBX #xx:8,Rd L L SUB.L ERs,ERd B L 6 SUB.L #xx:32,ERd DEC.B Rd W SUB.
Rev.7.00 Feb. 14, 2007 page 870 of 1108 REJ09B0089-0700 EXTU NEG CMP DIVXS W L 6 L B W CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd NEG.W Rd L W 4 CMP.W #xx:16,Rd EXTU.L ERd B CMP.B Rs,Rd L B 2 CMP.B #xx:8,Rd W W DIVXS.W Rs,ERd EXTU.W Rd B DIVXS.B Rs,Rd NEG.L ERd W DIVXU.W Rs,ERd 2 2 2 2 2 2 2 2 4 4 2 2 B DIVXU.
LDMAC ERs,MACH LDMAC STMAC MACL,ERd STMAC MACH,ERd LDMAC ERs,MACL CLRMAC CLRMAC STMAC Cannot be used in the chip MAC @ERn+, @ERm+ MAC 4 B TAS @ERd*3 TAS 2 L EXTS.L ERd 2 W Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa EXTS.W Rd EXTS Mnemonic ( of @ERd) @ERd-0→CCR set, (1)→ ( of ERd32) ( of ERd32)→ ( of Rd16) ( of Rd16)→ Operation ⎯ ⎯ ⎯ ⎯ 1 4 0 ⎯ 0 ⎯ [2] 1 0 ⎯ Advanced I H N Z V C ⎯ ⎯ No.
Rev.7.00 Feb. 14, 2007 page 872 of 1108 REJ09B0089-0700 NOT XOR OR AND W 4 W L 6 L AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd W L NOT.L ERd L XOR.L ERs,ERd NOT.W Rd L 6 XOR.L #xx:32,ERd B W XOR.W Rs,Rd NOT.B Rd W 4 XOR.W #xx:16,Rd OR.L ERs,ERd B L OR.L #xx:32,ERd B 2 L 6 OR.W Rs,Rd XOR.B Rs,Rd W OR.W #xx:16,Rd XOR.B #xx:8,Rd B W 4 OR.B Rs,Rd B 2 B OR.B #xx:8,Rd B 2 AND.
SHLL SHAR SHAL L L SHAL.L ERd SHAL.L #2,ERd B W W L L SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHAR.L #2,ERd SHLL.B #2,Rd L SHAR.L ERd B L SHAR.W #2,Rd SHLL.B Rd W W SHAR.W Rd B W SHAL.W #2,Rd SHAR.B #2,Rd W SHAL.W Rd B B SHAR.B Rd B SHAL.B #2,Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa SHAL.
Rev.7.00 Feb. 14, 2007 page 874 of 1108 REJ09B0089-0700 ROTXR ROTXL SHLR B W W L L ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L ROTXL.L #2,ERd B L ROTXL.L ERd ROTXR.B #2,Rd W ROTXL.W #2,Rd ROTXR.B Rd W ROTXL.W Rd SHLR.L #2,ERd B L SHLR.L ERd ROTXL.B #2,Rd L SHLR.W #2,Rd B W SHLR.W Rd ROTXL.B Rd B W SHLR.B #2,Rd B Operand Size SHLR.
ROTR ROTL W L L ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd B W W L L ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd B W ROTL.W Rd ROTR.B Rd B B ROTL.B #2,Rd 2 2 2 2 2 2 2 2 2 2 2 2 MSB C ⎯ ⎯ ¾ ⎯ ⎯ ⎯ ⎯ ¾ 1 ⎯ ⎯ ⎯ ⎯ ¾ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LSB LSB ¾ MSB C ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 0 0 0 0 I H N Z V C ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa ROTL.
Rev.7.00 Feb.
BTST B B B B B B BNOT Rn,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B BNOT Rn,Rd BNOT Rn,@aa:16 B BNOT #xx:3,@aa:32 B B BNOT #xx:3,@aa:16 B B BNOT #xx:3,@aa:8 BNOT Rn,@aa:8 B BNOT #xx:3,@ERd BNOT Rn,@ERd B BNOT #xx:3,Rd B BCLR Rn,@aa:32 BNOT 2 2 2 4 4 4 6 4 8 6 4 8 6 4 8 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa BCLR Mnemonic 4 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of
Rev.7.00 Feb.
BOR BIAND BAND BIST BST B B B B B B B B B B B B B B B B BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd B B BIST #xx:3,Rd B BST #xx:3,@aa:32 2 2 2 2 4 4 4 4 8 6 4 8 6 4 8 6 4 8 6 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa BST
Rev.7.00 Feb.
Bcc 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 Mnemonic Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa (6) Branch Instructions Branching Condition else next; PC←PC+d V=0
Bcc 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Mnemonic Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Addressing Mode/ Instruction Length (Bytes) Operation 2 3 2 3 2 3 2 3 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Rev.7.00 Feb.
RTS JSR BSR JMP 2 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS 2 4 4 ⎯ JMP @ERn 2 Operand Size #xx Rn @ERn Mnemonic 2 2 @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa 3 5 4 5 4 5 6 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PC→@-SP,PC←PC+d:8 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PC→@-SP,PC←@aa:8 PC→@-SP,PC←aa:24 PC→@-SP,PC←ERn PC→@-SP,PC←PC+d:16 PC←aa:24 PC←@aa:8 Advanced No.
W W W LDC @aa:32,CCR LDC @aa:32,EXR W LDC @(d:16,ERs),EXR LDC @aa:16,EXR W LDC @(d:16,ERs),CCR W W LDC @ERs,EXR LDC @aa:16,CCR W LDC @ERs,CCR W B LDC Rs,EXR LDC @ERs+,EXR B LDC Rs,CCR W B 4 LDC #xx:8,EXR LDC @ERs+,CCR B 2 LDC #xx:8,CCR LDC W ⎯ SLEEP SLEEP W ⎯ RTE RTE LDC @(d:32,ERs),EXR ⎯ Mnemonic LDC @(d:32,ERs),CCR Operand Size TRAPA #xx:2 2 2 4 4 10 10 6 6 4 4 #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ TRAPA @aa @(d,PC) @@aa 8 8 6 6 Operation I H N Z V C 1
NOP XORC ORC ANDC STC W W W W W W W B 2 B 4 B 2 B 4 B 2 B 4 ⎯ STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC #xx:8,CCR ANDC #xx:8,EXR ORC #xx:8,CCR ORC #xx:8,EXR XORC #xx:8,CCR XORC #xx:8,EXR NOP W STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) W W 2 4 10 10 6 6 4 4 8 8 6 6 W STC EXR,@ERd STC EXR,@(d:16,ERd) W STC CCR,@ERd STC CCR,@(d:16,ERd) B 4 B STC EXR,Rd 2 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa
Rev.7.00 Feb. 14, 2007 page 886 of 1108 REJ09B0089-0700 Notes: 1. 2. 3. [1] [2] [3] [4] [5] [6] [7] [8] [9] EEPMOV Addressing Mode/ Instruction Length (Bytes) Advanced 4+2n*2 4+2n*2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; ⎯ ⎯ EEPMOV.B EEPMOV.W The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4.
Appendix A Instruction Set A.2 Instruction Codes Table A.2 shows the instruction codes. Rev.7.00 Feb.
Rev.7.00 Feb. 14, 2007 page 888 of 1108 REJ09B0089-0700 Bcc BAND ANDC AND ADDX 0 7 7 7 6 6 4 5 4 5 B B B B B ⎯ ⎯ ⎯ ⎯ BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 0 BAND #xx:3,Rd 0 0 L AND.L ERs,ERd B 7 L AND.L #xx:32,ERd B 6 W AND.W Rs,Rd ANDC #xx:8,EXR 7 AND.W #xx:16,Rd ANDC #xx:8,CCR 1 B W AND.B Rs,Rd E B B ADDX Rs,Rd AND.
Bcc Instruction 5 4 5 4 5 ⎯ ⎯ ⎯ ⎯ ⎯ BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 BPL d:16 4 4 ⎯ BPL d:8 5 5 ⎯ BVS d:16 ⎯ 4 ⎯ BVS d:8 ⎯ 5 ⎯ BVC d:16 BLT d:8 4 ⎯ BVC d:8 BGE d:16 5 ⎯ BEQ d:16 4 4 ⎯ BEQ d:8 5 5 ⎯ BNE d:16 ⎯ 4 ⎯ BNE d:8 ⎯ 5 ⎯ BCS d:16 (BLO d:16) BGE d:8 4 ⎯ BCS d:8 (BLO d:8) BMI d:16 5 ⎯ BCC d:16 (BHS d:16) 4 4 ⎯ BCC d:8 (BHS d:8) 5 5 ⎯ BLS d:16 ⎯ 4 ⎯ BLS d:8 ⎯ 5 ⎯ BHI d:16 BMI d:8 4 8 F 8 E 8 D 8 C 8 B 8 A 8
Rev.7.00 Feb.
BNOT BLD BIXOR BIST Instruction B B B B B B B BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 B BNOT #xx:3,@aa:16 B BNOT #xx:3,@aa:8 B BLD #xx:3,@aa:32 BNOT #xx:3,@ERd B BLD #xx:3,@aa:16 B B BNOT #xx:3,Rd B BLD #xx:3,@aa:8 B BIXOR #xx:3,@aa:32 BLD #xx:3,@ERd B BIXOR #xx:3,@aa:16 B B BLD #xx:3,Rd B B BIST #xx:3,@aa:32 BIXOR #xx:3,@aa:8 B BIST #xx:3,@aa:16 BIXOR #xx:3,@ERd B BIST #xx:3,@aa:8 B B BIST #xx:3,@ERd BIXOR #xx:3,Rd
Rev.7.00 Feb.
3 5 7 7 ⎯ ⎯ EEPMOV EEPMOV.B EEPMOV.W B B 1 5 B W 1 0 B 1 1 B 1 0 B 1 DIVXU.W Rs,ERd W DIVXS.W Rs,ERd L B DEC.L #2,ERd DIVXS.B Rs,Rd L DEC.L #1,ERd B A F F 1 1 1 0 F DIVXU.B Rs,Rd DIVXU DIVXS W B DEC.W #2,Rd DEC.B Rd DEC B B W DAS Rd DAS DEC.W #1,Rd DAA Rd DAA A 1 L CMP.L ERs,ERd 7 L CMP.L #xx:32,ERd D 1 W CMP.W Rs,Rd 9 7 W C CMP.W #xx:16,Rd rd B CMP.B Rs,Rd 1 B CMP.
Rev.7.00 Feb. 14, 2007 page 894 of 1108 REJ09B0089-0700 LDC JSR JMP INC EXTU EXTS Instruction 1 L EXTU.L ERd 0 0 W L INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.
L B W W W W W MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.B Rs,@ERd B B MOV.B @aa:32,Rd B B MOV.B @aa:16,Rd MOV.B Rs,@aa :16 B MOV.B @aa:8,Rd MOV.B Rs,@aa:8 B MOV.B @ERs+,Rd B B MOV.B @(d:32,ERs),Rd MOV.B Rs,@-ERd B MOV.B @(d:16,ERs),Rd B B MOV.B @ERs,Rd B B MOV.B Rs,Rd MOV.B Rs,@(d:32,ERd) B MOV.B #xx:8,Rd MOV MOV.
Rev.7.00 Feb. 14, 2007 page 896 of 1108 REJ09B0089-0700 W L L L L L L L L L L L L L L MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MULXU B W MULXU.B Rs,Rd MULXU.W Rs,ERd B W MOV.W Rs,@aa:16 W W MOV.W Rs,@-ERd MULXS.W Rs,ERd W MOV.W Rs,@(d:32,ERd) B W MOV.
ROTL PUSH POP ORC 0 1 1 1 1 1 B W W L L ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 L B ROTL.B Rd PUSH.L ERn 6 0 L W POP.L ERn PUSH.W Rn 6 W POP.W Rn 0 0 L OR.L ERs,ERd 0 7 L OR.L #xx:32,ERd B 6 W OR.W Rs,Rd B 7 W OR.W #xx:16,Rd ORC #xx:8,EXR 1 B ORC #xx:8,CCR C B 1 L NOT.L ERd OR.B Rs,Rd 1 W NOT.W Rd OR.B #xx:8,Rd 1 B OR 0 ⎯ NOT.B Rd 1 L NEG.L ERd NOP 1 W NEG.
Rev.7.00 Feb. 14, 2007 page 898 of 1108 REJ09B0089-0700 B W W L L SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd B SHAL.B Rd ⎯ SHAL 5 L ⎯ ROTXR.L #2, ERd RTS 5 L ROTXR.L ERd RTS 1 W ROTXR.W #2, Rd RTE W 1 1 1 1 1 1 1 1 1 1 ROTXR.W Rd 1 1 B L ROTXL.L #2, ERd 1 ROTXR.B #2, Rd L ROTXL.L ERd 1 B W ROTXL.W #2, Rd 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 4 6 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 1st byte ROTXR.B Rd W ROTXL.
0 0 0 0 0 0 0 0 W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W W STC.W CCR,@ERd STC.W CCR,@-ERd STC.W EXR,@-ERd 0 0 B W STC.B EXR,Rd 0 1 L ⎯ SHLR.L #2, ERd B 1 L SHLR.L ERd STC.B CCR,Rd 1 W SHLR.W #2, Rd STC 1 W SHLR.W Rd SLEEP 1 B 1 L SHLL.L #2, ERd SHLR.B #2, Rd 1 L SHLL.L ERd 1 1 W SHLL.W #2, Rd B 1 W SHLL.W Rd SHLR.B Rd 1 B 1 L SHAR.L #2, ERd SHLL.B #2, Rd 1 L SHAR.
Rev.7.00 Feb. 14, 2007 page 900 of 1108 REJ09B0089-0700 0 5 B ⎯ B B W W L L TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.
B B XORC #xx:8,EXR Size XORC #xx:8,CCR Mnemonic 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte General Register ER0 ER1 · · · ER7 Register Field 000 001 · · · 111 Address Register 32-Bit Register 0000 0001 · · · 0111 1000 1001 · · · 1111 Register Field R0 R1 · · · R7 E0 E1 · · · E7 General Register 16-Bit Register The register fields specify general registers as follows.
Rev.7.00 Feb. 14, 2007 page 902 of 1108 REJ09B0089-0700 1 2 3 BL XOR BSR BCS AND RTE BNE BST TRAPA BEQ SUB ADD MOV OR XOR AND MOV C D E F CMP SUBX B BVS 9 Table A.3(2) MOV Table A.3(2) A Note: * Cannot be used in the chip. 8 BVC MOV.B Table A.3(2) LDC 7 BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD OR RTS BCC AND ANDC 6 ADDX BTST DIVXU BLS XOR XORC 5 9 BCLR MULXU BHI OR ORC 4 Table A.3(2) Table A.3(2) JMP BPL Table A.3(2) Table A.
ROTXR 13 SUBS DAS BRA MOV MOV MOV 1B 1F 58 6A 79 7A ADD CMP CMP MOV ADD BHI BRN 2 BCC ROTXR ROTXL SHLR SHLL STC 4 LDC SUB SUB OR OR Table * A.3(4) MOVFPE BLS NOT STM 3 BL 2nd byte BH Table A.3(4) AL Note: * Cannot be used in the chip.
Rev.7.00 Feb. 14, 2007 page 904 of 1108 REJ09B0089-0700 BSET BNOT BNOT BNOT BNOT DIVXS 1 AL BCLR BCLR BCLR BCLR MULXS 2 BH 3 BTST BTST BTST BTST XOR 5 DH AND 6 DL 4th byte 7 BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST OR 4 CL 3rd byte CH DIVXS BL 2nd byte Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
AH BSET 0 BNOT BNOT 1 AL 1st byte BSET 1 0 BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification. 6A38aaaaaaaa7* 6A38aaaaaaaa6* 6A30aaaaaaaa7* 6A30aaaaaaaa6* AHALBHBL ...
Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle.
Appendix A Instruction Set Table A.
Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation I K M N Instruction Mnemonic ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND.B #xx:8,Rd 1 AND ANDC BAND Bcc AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I Bcc BVS d:8 2 BCLR BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 J L BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BIAND BIAND #xx:3,Rd 1 BILD BIOR BIST BIXOR BLD J L BIAND #xx:3,@ERd 2 1 BIAND #xx:3,@aa:8 2 1 BIAND #xx:3,@aa:16 3 1 BIAND #xx:3,@aa:32 4 1 BILD #xx:3,Rd 1 BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BNOT BNOT #xx:3,Rd 1 BOR BSET J L BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BNOT #xx:3,@aa:32 4 2 BNOT Rn,Rd 1 BNOT Rn,@ERd 2 2 BNOT Rn,@aa:8 2 2 BNOT Rn,@aa:16 3 2 BNOT Rn,@aa:32 4 2 BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 1 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #xx:3,@aa:3
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BTST BTST #xx:3,Rd 1 BXOR CLRMAC CMP BTST #xx:3,@ERd 2 1 2 1 BTST #xx:3,@aa:16 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLR
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I EEPMOV EEPMOV.B 2 EEPMOV.W 2 EXTS EXTS.W Rd 1 EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 EXTU INC JMP JSR LDC INC.B Rd 1 INC.W #1/2,Rd 1 INC.
Appendix A Instruction Set Branch Instruction Address Fetch Read Word Data Access Internal Operation K M N Instruction Mnemonic I LDM LDM.L @SP+, (ERn-ERn+1) 2 4 1 LDM.L @SP+, (ERn-ERn+2) 2 6 1 LDM.L @SP+, (ERn-ERn+3) 2 8 1 LDMAC ERs,MACH Cannot be used in the chip LDMAC J Byte Stack Data Operation Access L LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ Cannot be used in the chip MOV MOV.B #xx:8,Rd 1 MOV.B Rs,Rd 1 MOV.B @ERs,Rd 1 1 MOV.B @(d:16,ERs),Rd 2 1 MOV.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I MOV MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.W Rs,@-ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.W Rs,@aa:32 3 1 MOVFPE MOV.L #xx:32,ERd 3 MOV.L ERs,ERd 1 J L MOV.L @ERs,ERd 2 2 MOV.L @(d:16,ERs),ERd 3 2 MOV.L @(d:32,ERs),ERd 5 2 MOV.L @ERs+,ERd 2 2 MOV.L @aa:16,ERd 3 2 MOV.L @aa:32,ERd 4 2 MOV.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I OR OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 OR.L #xx:32,ERd 3 ORC POP PUSH ROTL ROTR ROTXL J L OR.L ERs,ERd 2 ORC #xx:8,CCR 1 ORC #xx:8,EXR 2 POP.W Rn 1 1 1 POP.L ERn 2 2 1 PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 ROTL.B Rd 1 ROTL.B #2,Rd 1 ROTL.W Rd 1 ROTL.W #2,Rd 1 ROTL.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I ROTXR ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 ROTXR.L ERd 1 J L ROTXR.L #2,ERd 1 RTE RTE 2 2/3*1 1 RTS RTS 2 2 1 SHAL SHAL.B Rd 1 SHAL.B #2,Rd 1 SHAR SHLL SHLR SLEEP SHAL.W Rd 1 SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.B Rd 1 SHAR.B #2,Rd 1 SHAR.W Rd 1 SHAR.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I STC STC.B CCR,Rd 1 STM STMAC STC.B EXR,Rd 1 STC.W CCR,@ERd 2 STC.W EXR,@ERd J L 1 2 1 STC.W CCR,@(d:16,ERd) 3 1 STC.W EXR,@(d:16,ERd) 3 1 STC.W CCR,@(d:32,ERd) 5 1 STC.W EXR,@(d:32,ERd) 5 1 STC.W CCR,@-ERd 2 1 1 STC.W EXR,@-ERd 2 1 1 STC.W CCR,@aa:16 3 1 STC.W EXR,@aa:16 3 1 STC.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I XOR XOR.B #xx:8,Rd 1 XORC XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC #xx:8,CCR 1 XORC #xx:8,EXR 2 J L Notes: 1. The number of state cycles is 2 when EXR is invalid, and 3 when EXR is valid. 2. When n bytes of data are transferred. 3.
Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle.
Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1st byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.
Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.
R:W NEXT R:W 2nd R:W 2nd R:W 2nd BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W 2nd BPL d:16 R:W 2nd R:W 2nd BVS d:16 BLE d:16 R:W 2nd BVC d:16 R:W 2nd R:W 2nd BEQ d:16 BGT d:16 R:W 2nd BNE d:16 R:W 2nd R:W 2nd BCS d:16 (BLO d:16) BLT d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd R:W 2nd BLS d:16 BGE d:16 R:W 2nd BHI d:16 R:W 2nd R:W 2nd BRN d:16 (BF d:16) BMI d:16 1 R:W NEXT R:W 2nd Instruction BLE d:8 BRA d:16 (BT d:16) R:B:M EA R:B:M EA R:W 3rd 2 R:W EA
Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #x
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3
R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd Rev.7.00 Feb.
R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.
R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@−ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.
MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@−ERd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.
1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.
1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd Instruction ROTXR.L #2,ERd RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.
Rev.7.00 Feb. 14, 2007 page 932 of 1108 REJ09B0089-0700 R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.
R:W*6 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state R:W NEXT R:W VEC+2 2 R:W NEXT W:W stack (EXR) 5 R:W:M VEC 6 R:W VEC+2 7 9 Internal operation, R:W*7 1 state 8 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4.
Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below.
Appendix A Instruction Set Table A.7 Instruction Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADD N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADDX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm Z = Rm · Rm–1 · ......
Appendix A Instruction Set Instruction H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 CMP N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS — — — N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ......
Appendix A Instruction Set Instruction H MOV — N Z V C Definition 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 MOVFPE Cannot be used in the chip MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ...... · R0 MULXU — — — — — NEG H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP — — — — — NOT — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ORC Stores the corresponding bits of the result.
Appendix A Instruction Set Instruction H ROTXL — N Z V C 0 Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE Stores the corresponding bits of the result. RTS — — — — — SHAL — N = Rm Z = Rm · Rm–1 · ......
Appendix A Instruction Set Instruction H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUB N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUBX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 TRAPA — — — — — XOR — 0 — N = Rm Z = Rm · Rm–1 · ......
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers Address Register Name Bit 7 H'FE90 TCR4 — CCLR1 CCLR0 CKEG H'FE91 TMDR4 — — — — H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 H'FE94 TIER4 TTGE — TCIEU TCIEV H'FE95 TSR4 TCFD — TCFU H'FE96 TCNT4 Bit 6 Bit 5 Data Bus Width Bit 2 Bit 1 Bit 0 Module Name CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 bits MD3 MD2 MD1 MD0 IOA3 IOA2 IOA1 IOA0 — — TGIEB TGIEA TCFV — — TGFB TGFA TPU5 16 bits Bit 4 Bit 3 H'FE97 H'FE98 TGR4A H'FE99 H'FE9A
Appendix B Internal I/O Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FEC4 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC5 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC6 IPRC — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC7 IPRD — IPR6 IPR5 IPR4 — — — — H'FEC8 IPRE — — — — — IPR2 IPR1 IPR0 H'FEC9 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FECA IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FECB IPRH — IPR6
Appendix B Internal I/O Registers Address Register Name H'FF42 3 SYSCR2* — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — FLSHE — — — — — Module Name Flash memory Data Bus Width 8 bits H'FF44 Reserved — — — — — — Reserved — H'FF45 PFCR1 CSS17 CSS36 PF1CS5S PF0CS4S A23E A22E A21E A20E Ports 8 bits H'FF50 PORT1 P17 P16 P15 P13 P12 P11 P10 H'FF51 PORT2 P27 P26 P25 P24 P23 P22 P21 P20 H'FF52 PORT3 — — P35 P34 P33 P32 P31 P30 H'FF53
Appendix B Internal I/O Registers Address Register Name H'FF78 SMR0 H'FF79 BRR0 H'FF7A SCR0 H'FF7B TDR0 H'FF7C SSR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C/A/ GM*3 CHR/ 4 BLK* PE O/E STOP/ 5 BCP1* MP/ 6 BCP0* CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS*7 PER TEND MPB MPBT H'FF7D RDR0 H'FF7E SCMR0 — — — — SDIR SINV — SMIF H'FF80 SMR1 C/A/ GM*4 CHR/ 5 BLK* PE O/E STOP/ 6 BCP1* MP/ 7 BCP0* CKS1 CKS0 H'FF81 BRR
Appendix B Internal I/O Registers Address Register Name H'FFA4 DADR0 H'FFA5 DADR1 Bit 7 Bit 6 Bit 5 Bit 4 — Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width D/A converter 8 bits 8 bits H'FFA6 DACR01 DAOE1 DAOE0 DAE — — — — H'FFAC PFCR2 — — CS167E CS25E ASOD — — — Ports H'FFB0 TCR0 CMIEB CMIEA OVIE CCLR0 CKS2 CKS1 CKS0 8-bit timer 16 bits channel 0, 1 CCLR1 H'FFB1 TCR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFB2 TCSR0 CMFB CMFA OVF AD
Appendix B Internal I/O Registers Register Name Bit 7 Bit 6 Bit 5 9 H'FFC8* FLMCR1 FWE SWE ESU PSU EV PV E P H'FFC9*9 FLMCR2 FLER — — — — — — — H'FFCA* EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H'FFCB* EBR2 — — — — — — EB9 EB8 E P Address 9 9 H'FFC8 *10 FLMCR1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FWE SWE ESU PSU EV PV 10 H'FFC9* FLMCR2 FLER — — — — — — — H'FFCA* EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H'FFCB* EBR2 — — — — EB11 EB10 EB9 EB
Appendix B Internal I/O Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Data Bus Width Bit 2 Bit 1 Bit 0 Module Name TPU0 16 bits TPU1 16 bits H'FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFD1 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0 H'FFD2 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FFD3 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FFD4 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H'FFD5 TSR0 — — — TCFV
Appendix B Internal I/O Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TPU2 H'FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFF1 TMDR2 — — — — MD3 MD2 MD1 MD0 H'FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FFF4 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FFF5 TSR2 TCFD — TCFU TCFV — — TGFB TGFA H'FFF6 TCNT2 Data Bus Width 16 bits H'FFF7 H'FFF8 TGR2A H'FFF9 H'FFFA TGR2B H'FFFB N
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* Bus controller Bus width control register ABWCR R/W H'FF/H'00* H'FED0 Access state control register ASTCR R/W H'FF H'FED1 Wait control register H WCRH R/W H'FF H'FED2 Wait control register L WCRL R/W H'FF H'FED3 8-bit timer 0 8-bit timer 1 5 Bus control register H BCRH R/W H'D0 H'FED4 Bus control register L BCRL R/W H'3C H'FED5 Timer control register 0 TCR0 R/W H'00 H'FFB0
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* SCI0 Serial mode register 0 SMR0 R/W H'00 H'FF78 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF H'FF7B Serial status register 0 SSR0 2 R/(W)* H'84 H'FF7C Receive data register 0 RDR0 R H'00 H'FF7D Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E Serial mode register 1 SMR1 R/W H'00 H'FF80 Bit r
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* All SMCI channels Module stop control register MSTPCR R/W H'3FFF H'FF3C ADC A/D data register AH ADDRAH R H'00 H'FF90 A/D data register AL ADDRAL R H'00 H'FF91 A/D data register BH ADDRBH R H'00 H'FF92 A/D data register BL ADDRBL R H'00 H'FF93 A/D data register CH ADDRCH R H'00 H'FF94 A/D data register CL ADDRCL R H'00 H'FF95 A/D data register DH ADDRDH R H'00 H'FF96 A/D
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* TPU1 Timer I/O control register 1 TIOR1 R/W H'00 H'FFE2 Timer interrupt enable register 1 TIER1 R/W H'FFE4 Timer status register 1 TSR1 H'40 2 * R/(W) H'C0 Timer counter 1 TCNT1 R/W H'FFE6 TPU2 TPU3 TPU4 H'0000 H'FFE5 Timer general register 1A TGR1A R/W H'FFFF H'FFE8 Timer general register 1B TGR1B R/W H'FFFF H'FFEA Timer control register 2 TCR2 R/W H'00 H'FFF0 Timer mode reg
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* TPU5 Timer control register 5 TCR5 R/W H'00 H'FEA0 Timer mode register 5 TMDR5 R/W H'C0 H'FEA1 Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2 Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4 H'FEA5 All TPU channels Flash memory Timer status register 5 TSR5 2 R/(W) * H'C0 Timer counter 5 TCNT5 R/W H'0000 H'FEA6 Timer general register 5A TGR5A R/W H'FFFF H'FEA8 Timer
Appendix B Internal I/O Registers Module Register 1 Abbreviation R/W Initial Value Address* Standby control register Powerdown state Module stop control register H SBYCR R/W H'08 H'FF38 MSTPCRH R/W H'3F H'FF3C Module stop control register L MSTPCRL R/W H'FF H'FF3D Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Port function control register 1 PFCR1 R/W H'0F H'FF45 Port 2 data directi
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* Port E Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D R/W H'00 H'FF74 Port E MOS pull-up control register PEPCR Port F Port G Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
Appendix B Internal I/O Registers 14. 15. 16. 17. 18. 19. 20. 21. In the H8S/2319 F-ZTAT, the EB11 to EB0 bits are initialized to 0 when the SWE1 bit is not set to 1, and the EB15 to EB12 bits are initialized to 0 when the SWE2 bit is not set to 1. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be used on these registers, with the access requiring two states (Applies to the F-ZTAT versions but the H8S/2319C F-ZTAT). The SYSCR2 register can only be used in the F-ZTAT versions.
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers MRB—DTC Mode Register B Bit : Initial value : H'F800—H'FBFF DTC 7 6 5 4 3 2 1 0 CHNE DISEL CHNS ⎯ ⎯ ⎯ ⎯ ⎯ Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined ⎯ Read/Write : ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Reserved Only 0 should be written to these bits DTC Interrupt Select 0 After DTC data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After DTC data transfer ends, the CPU interrupt is enabled DTC
Appendix B Internal I/O Registers DAR—DTC Destination Address Register Bit : 23 22 21 20 H'F800—H'FBFF 19 --- 4 3 DTC 2 1 0 --Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ⎯ ⎯ ⎯ ⎯ Unde- Unde- Unde- Unde- Undefined fined fined fined fined --- ⎯ ⎯ --- ⎯ ⎯ ⎯ ⎯ Specifies DTC transfer data destination address CRA—DTC Transfer Count Register A Bit : Initial value : Read/Write : 15 14 13 12 11 H'F800—H'FBFF 10 9 8 7 6 5 4 3 DTC
Appendix B Internal I/O Registers TCR3—Timer Control Register 3 7 6 5 CCLR2 CCLR1 CCLR0 Initial value : 0 0 0 0 Read/Write : R/W R/W R/W R/W Bit : H'FE80 4 3 TPU3 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 R/W R/W R/W R/W CKEG1 CKEG0 Timer Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/102
Appendix B Internal I/O Registers TMDR3—Timer Mode Register 3 H'FE81 TPU3 7 6 5 4 3 2 1 0 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ R/W R/W R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Notes: 1. MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR3H—Timer I/O Control Register 3H H'FE82 7 6 5 4 3 2 1 0 Initial value : IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : TPU3 TGR3A I/O Control 0 0 0 0 1 1 0 TGR3A Output disabled is output compare Initial output is register 0 output 1 1 0 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 0 outpu
Appendix B Internal I/O Registers TIOR3L—Timer I/O Control Register 3L Bit H'FE83 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU3 TGR3C I/O Control 0 0 0 1 1 0 1 1 0 1 0 TGR3C Output disabled is output 1 compare Initial output is *1 0 output 0 register 1 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 0
Appendix B Internal I/O Registers TIER3—Timer Interrupt Enable Register 3 Bit : H'FE84 TPU3 7 6 5 4 3 2 1 0 TTGE ⎯ ⎯ TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ ⎯ R/W R/W R/W R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled TGR Inter
Appendix B Internal I/O Registers TSR3—Timer Status Register 3 Bit : H'FE85 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT=TGRA while TGRA is functioning as
Appendix B Internal I/O Registers TCNT3—Timer Counter 3 Bit H'FE86 TPU3 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit H'FE88 H'FE8A H'FE8C H'FE8E TPU3 TPU3 TPU3 TPU3 : 15 14 13 12 11 10 9 8 7 6 5
Appendix B Internal I/O Registers TCR4—Timer Control Register 4 Bit : 7 6 5 ⎯ CCLR1 CCLR0 H'FE90 4 3 CKEG1 CKEG0 TPU4 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ R/W R/W R/W R/W R/W R/W R/W Timer Prescaler 0 0 1 1 0 1 Clock Edge 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on
Appendix B Internal I/O Registers TMDR4—Timer Mode Register 4 H'FE91 TPU4 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR4—Timer I/O Control Register 4 Bit H'FE92 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU4 TGR4A I/O Control 0 0 0 1 1 0 1 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1
Appendix B Internal I/O Registers TIER4—Timer Interrupt Enable Register 4 Bit : H'FE94 TPU4 7 6 5 4 3 2 1 0 TGIEA TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ R/W R/W ⎯ ⎯ R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interrup
Appendix B Internal I/O Registers TSR4—Timer Status Register 4 Bit : H'FE95 7 6 5 4 3 2 1 0 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R ⎯ R/(W)* R/(W)* ⎯ ⎯ R/(W)* R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as ou
Appendix B Internal I/O Registers TCNT4—Timer Counter 4 Bit H'FE96 TPU4 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers TCR5—Timer Control Register 5 Bit : 7 6 5 ⎯ CCLR1 CCLR0 H'FEA0 4 3 CKEG1 CKEG0 TPU5 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin in
Appendix B Internal I/O Registers TMDR5—Timer Mode Register 5 H'FEA1 TPU5 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR5—Timer I/O Control Register 5 Bit H'FEA2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU5 TGR5A I/O Control 0 0 0 1 1 0 1 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 × 0 1 0
Appendix B Internal I/O Registers TIER5—Timer Interrupt Enable Register 5 Bit : H'FEA4 TPU5 7 6 5 4 3 2 1 0 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ R/W R/W ⎯ ⎯ R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR5—Timer Status Register 5 Bit : H'FEA5 7 6 5 4 3 2 1 0 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R ⎯ R/(W)* R/(W)* ⎯ ⎯ R/(W)* R/(W)* TPU5 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as ou
Appendix B Internal I/O Registers TCNT5—Timer Counter 5 Bit H'FEA6 TPU5 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers P2DDR—Port 2 Data Direction Register Bit : 7 6 H'FEB1 5 4 3 2 Port 2 0 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register Bit : Initial value : 7 6 ⎯ ⎯ Undefined Undefined ⎯ Read/Write : ⎯ H'FEB2 5 4 3 2 Port 3 0 1 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR 0 0 0 0 0 0
Appendix B Internal I/O Registers PBDDR—Port B Data Direction Register Bit : 7 6 5 H'FEBA 4 3 2 Port B 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port B pins PCDDR—Port C Data Direction Register H'FEBB Port C Bit : Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W 7 6 5 4 3 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR
Appendix B Internal I/O Registers PEDDR—Port E Data Direction Register Bit : 7 6 5 H'FEBD 4 3 2 Port E 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port E pins PFDDR—Port F Data Direction Register Bit : 7 6 5 H'FEBE 4 3 2 Port F 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6* Initial value : 1 0 0 0 0 0 0 0 Read/Write
Appendix B Internal I/O Registers PGDDR—Port G Data Direction Register Bit : 7 6 5 ⎯ ⎯ ⎯ H'FEBF 4 3 2 Port G 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 4 and 5 Initial value : Undefined Undefined Undefined Read/Write : ⎯ ⎯ ⎯ 1 0 0 0 0 W W W W W Modes 6 and 7* Initial value : Undefined Undefined Undefined Read/Write : ⎯ ⎯ ⎯ 0 0 0 0 0 W W W W W Specify input or output for individual port G pins Note: * Modes 6 and 7 cannot be used in the ROMless versions.
Appendix B Internal I/O Registers IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Interrupt Priority Register I IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K Bit : H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE Interr
Appendix B Internal I/O Registers ABWCR—Bus Width Control Register Bit H'FED0 Bus Controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W : Modes 5 to 7* Initial value : R/W : Mode 4 Area 7 to 0 Bus Width Control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) Note: *
Appendix B Internal I/O Registers WCRH—Wait Control Register H : H'FED2 Bus Controller 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit Area 4 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 5 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 pr
Appendix B Internal I/O Registers WCRL—Wait Control Register L Bit : H'FED3 Bus Controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 0 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 1 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 pr
Appendix B Internal I/O Registers BCRH—Bus Control Register H H'FED4 7 6 ICIS1 ICIS0 Initial value : 1 1 0 1 Read/Write : R/W R/W R/W R/W Bit : 5 4 3 Bus Controller 2 1 0 ⎯ ⎯ ⎯ 0 0 0 0 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 Reserved Only 0 should be written to these bits Burst Cycle Select 0 0 Max. 4 words in burst access 1 Max.
Appendix B Internal I/O Registers BCRL—Bus Control Register L H'FED5 Bus Controller 7 6 5 4 3 2 1 0 BRLE BREQOE EAE ⎯ ⎯ ⎯ ⎯ WAITE Initial value : 0 0 1 1 1 1 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : WAIT Pin Enable 0 Wait input by WAIT pin disabled 1 Wait input by WAIT pin enabled Reserved Only 0 should be written to this bit. Reserved Only 1 should be written to these bits.
Appendix B Internal I/O Registers RAMER—RAM Emulation Register Bit : H'FEDB Flash Memory (Valid only in F-ZTAT versions*) 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W RAM Select, Flash Memory Area Select RAMS RAM2 RAM1 RAM0 RAM Area Block Name 0 × × × H'FFDC00 to H'FFEBFF RAM area, 4 kbytes 1 0 0 0 H'000000 to H'000FFF EB0 (4 kbytes) 1 H'001000 to H'001FFF EB1 (4 kbytes) 0 H'002000 t
Appendix B Internal I/O Registers ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L H'FF2C H'FF2D Interrupt Controller Interrupt Controller ISCRH Bit : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 IRQ7 to IRQ4 Sense Control A, B ISCRL Bit : 7 6 5 4 3 2 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial val
Appendix B Internal I/O Registers IER—IRQ Enable Register Bit : H'FF2E Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W IRQn Enable 0 IRQn interrupt disabled 1 IRQn interrupt enabled (n = 7 to 0) Rev.7.00 Feb.
Appendix B Internal I/O Registers ISR—IRQ Status Register Bit : H'FF2F Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Bit n IRQnF Description 0 [Clearing conditions] 1 (Initial value) • When 0 is written to IRQnF after reading IRQnF = 1 • When interrupt exception handl
Appendix B Internal I/O Registers DTCERA to DTCERF—DTC Enable Registers Bit : H'FF30 to H'FF34 DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended 1 DTC activation by this interrup
Appendix B Internal I/O Registers DTVECR—DTC Vector Register Bit : 7 6 H'FF37 5 4 3 DTC 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended • When 0 is writte
Appendix B Internal I/O Registers SBYCR—Standby Control Register Bit : H'FF38 Power-Down State 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE ⎯ ⎯ IRQ37S Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W R/W R/W R/W ⎯ ⎯ R/W IRQ37 Software Standby Clear Select 0 IRQ3 to IRQ7 cannot be used as software standby mode clearing sources 1 IRQ3 to IRQ7 can be used as software standby mode clearing sources Output Port Enable 0 In software standby mode, address bus and bus contr
Appendix B Internal I/O Registers SYSCR—System Control Register Bit : H'FF39 7 6 5 4 ⎯ ⎯ INTM1 INTM0 3 MCU 2 NMIEG LWROD 1 0 ⎯ RAME Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W ⎯ R/W R/W R/W R/W R/W R/W RAM Enable 0 On-chip RAM disabled 1 On-chip RAM enabled Reserved Only 0 should be written to this bit LWR Output Disable 0 PF3 is designated as LWR output pin 1 PF3 is designated as I/O port, and does not function as LWR output pin NMI Input Edge Select 0 Fal
Appendix B Internal I/O Registers SCKCR—System Clock Control Register Bit : H'FF3A Clock Pulse Generator 7 6 5 4 3 2 1 0 PSTOP ⎯ DIV ⎯ ⎯ SCK2 SCK1 SCK0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W ⎯ ⎯ R/W R/W R/W Division Ratio Select Reserved Only 0 should be written to this bit System Clock Select DIV = 0 0 0 1 1 0 1 DIV = 1 0 Bus master is in high-speed mode Bus master is in high-speed mode 1 Medium-speed clock is φ/2 Clock supplied to entire
Appendix B Internal I/O Registers MDCR—Mode Control Register Bit : H'FF3B MCU 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ MDS2 MDS1 MDS0 Initial value : 1 0 0 0 0 ⎯* ⎯* ⎯* Read/Write : ⎯ ⎯ ⎯ ⎯ ⎯ R R R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH—Module Stop Control Register H MSTPCRL—Module Stop Control Register L H'FF3C H'FF3D MSTPCRH Bit Power-Down State Power-Down State MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial valu
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 H'FF42 Flash Memory (Valid only in F-ZTAT versions) Bit : 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ FLSHE ⎯ ⎯ ⎯ Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W ⎯ ⎯ ⎯ (R/W) In the H8S/2319 and H8S/2319C, this bit is reserved and should be written with 0.
Appendix B Internal I/O Registers PFCR1—Port Function Control Register 1 Bit : 7 6 CSS17 CSS36 H'FF45 4 5 PF1CS5S PF0CS4S Port 3 2 1 0 A23E A22E A21E A20E Initial value : 0 0 0 0 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Address 20 Output Enable*1 0 P10DR is output when P10DDR = 1 1 A20 is output when P10DDR = 1 Address 21 Output Enable*1 0 P11DR is output when P11DDR = 1 1 A21 is output when P11DDR = 1 Address 22 Output Enable*1 0 P12DR is output whe
Appendix B Internal I/O Registers PORT1—Port 1 Register Bit : H'FF50 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value : ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* Read/Write : R R R R R R R R State of port 1 pins Note: * Determined by the state of pins P17 to P10.
Appendix B Internal I/O Registers PORT4—Port 4 Register Bit : H'FF53 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value : ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* Read/Write : R R R R R R R R State of port 4 pins Note: * Determined by the state of pins P47 to P40.
Appendix B Internal I/O Registers PORTC—Port C Register Bit : H'FF5B Port C 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial value : ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* Read/Write : R R R R R R R R State of port C pins Note: * Determined by the state of pins PC7 to PC0.
Appendix B Internal I/O Registers PORTF—Port F Register Bit : H'FF5E Port F 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Initial value : ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* ⎯* Read/Write : R R R R R R R R State of port F pins Note: * Determined by the state of pins PF7 to PF0.
Appendix B Internal I/O Registers P2DR—Port 2 Data Register : Bit H'FF61 Port 2 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port 2 pins (P27 to P20) P3DR—Port 3 Data Register Bit : H'FF62 7 6 5 4 3 2 1 0 ⎯ ⎯ P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Initial value : Undefined Undefined Read/
Appendix B Internal I/O Registers PBDR—Port B Data Register Bit : 7 PB7DR H'FF6A 6 5 4 3 Port B 2 PB6DR PB5DR PB4DR PB3DR PB2DR 1 0 PB1DR PB0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port B pins (PB7 to PB0) PCDR—Port C Data Register : Bit 6 7 PC7DR H'FF6B 5 3 4 Port C 1 2 PC6DR PC5DR PC4DR PC3DR PC2DR 0 PC1DR PC0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W
Appendix B Internal I/O Registers PEDR—Port E Data Register Bit : 6 7 PE7DR H'FF6D 5 PE6DR PE5DR 4 3 Port E 1 2 PE4DR PE3DR PE2DR 0 PE1DR PE0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port E pins (PE7 to PE0) PFDR—Port F Data Register Bit : H'FF6E Port F 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR 0 0 0 0 R/W R/W R/W R/W Initial value : 0 0 0 0 Read/Write : R/W
Appendix B Internal I/O Registers PAPCR—Port A MOS Pull-Up Control Register Bit : Initial value : Read/Write : 7 6 5 4 ⎯ ⎯ ⎯ ⎯ H'FF70 3 ⎯ ⎯ 2 0 1 PA3PCR PA2PCR PA1PCR PA0PCR 0 0 0 0 R/W R/W R/W R/W Undefined Undefined Undefined Undefined ⎯ Port A ⎯ Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis PBPCR—Port B MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF71 3 2 Port B 0 1 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR In
Appendix B Internal I/O Registers PDPCR—Port D MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF73 3 2 Port D 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis PEPCR—Port E MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF74 3 2 Port E 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initia
Appendix B Internal I/O Registers PAODR—Port A Open Drain Control Register Bit : Initial value : Read/Write : H'FF77 7 6 5 4 ⎯ ⎯ ⎯ ⎯ 3 ⎯ ⎯ ⎯ 1 0 PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined Undefined Undefined ⎯ 2 Port A 0 0 0 0 R/W R/W R/W R/W Controls the PMOS on/off status for each port A pin (PA3 to PA0) Rev.7.00 Feb.
Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : H'FF78 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity*1 1 Odd parity*2 Notes:
Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : H'FF78 Smart Card Interface 0 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Base Clock Pulse BCP1 BCP0 0 1 Base Clock Pulse 0 32 clocks 1 64 clocks 0 372 clocks 1 256 clocks Parity Mode 0 Even parity*1 1 Odd parity*2 Notes: 1.
Appendix B Internal I/O Registers BRR0—Bit Rate Register 0 Bit H'FF79 SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: For details, see section 12.2.8, Bit Rate Register (BRR). Rev.7.00 Feb.
Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : H'FF7A 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W SCI0 Clock Enable 0 0 1 1 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal c
Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : H'FF7A 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Smart Card Interface 0 Clock Enable SMCR SMR SMIF GM SCR setting CKE1 SCK pin function CKE0 See SCI specification 0 1 0 0 0 Operates as port I/O pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1
Appendix B Internal I/O Registers TDR0—Transmit Data Register 0 Bit : 7 6 H'FF7B 5 4 SCI0, Smart Card Interface 0 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev.7.00 Feb.
Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : H'FF7C 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received* 1 [Setting condition] When data
Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : H'FF7C 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Smart Card Interface 0 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received* 1 [S
Appendix B Internal I/O Registers RDR0—Receive Data Register 0 Bit H'FF7D SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : H'FF7E SCI0, Smart Card Interface 0 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W ⎯ R/W Smart Card Interface Mode Select 0 Smart card in
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : H'FF80 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity*1 1 Odd parity*2 Notes:
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : H'FF80 Smart Card Interface 1 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Base Clock Pulse BCP1 BCP0 0 1 Base Clock Pulse 0 32 clocks 1 64 clocks 0 372 clocks 1 256 clocks Parity Mode (Set to 1 when using the smart card interface) 0 Ev
Appendix B Internal I/O Registers BRR1—Bit Rate Register 1 Bit : 7 H'FF81 6 5 4 SCI1, Smart Card Interface 1 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: For details, see section 12.2.8, Bit Rate Register (BRR). Rev.7.00 Feb.
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : H'FF82 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W SCI1 Clock Enable 0 0 1 1 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal c
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : H'FF82 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Smart Card Interface 1 Clock Enable SMCR SMR SMIF GM SCR setting CKE1 SCK pin function CKE0 See SCI specification 0 1 0 0 0 Operates as port I/O pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1
Appendix B Internal I/O Registers TDR1—Transmit Data Register 1 Bit : 7 6 H'FF83 5 4 SCI1, Smart Card Interface 1 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev.7.00 Feb.
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : H'FF84 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W SCI1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received* 1 [Setting condition] Wh
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : H'FF84 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Smart Card Interface 1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received* 1 [S
Appendix B Internal I/O Registers RDR1—Receive Data Register 1 Bit : 7 H'FF85 6 5 4 SCI1, Smart Card Interface 1 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : H'FF86 SCI1, Smart Card Interface 1 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W ⎯ R/W Smart Card Interface Mode Select 0 Smart card in
Appendix B Internal I/O Registers ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL Bit : 15 14 13 12 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 11 10 9 8 7 6 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD
Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register Bit : H'FF98 A/D Converter 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel Select Note: These bits select the analog input channel(s). Ensure that conversion is halted (ADST = 0) before making a channel setting.
Appendix B Internal I/O Registers ADCR—A/D Control Register Bit : H'FF99 A/D Converter 7 6 5 4 3 2 1 0 TRGS1 TRGS0 ⎯ ⎯ CKS1 ⎯ ⎯ ⎯ Initial value : 0 0 1 1 1 1 1 1 Read/Write : R/W R/W ⎯ ⎯ R/W R/W ⎯ ⎯ Reserved Only 1 should be written to this bit. Clock Select CKS1 is used in combination with CKS, bit 3 in ADCSR. Bit 3 ADCSR Bit 3 CKS1 CKS 0 0 Conversion time = 530 states (max.) 1 Conversion time = 68 states (max.) 0 Conversion time = 266 states (max.
Appendix B Internal I/O Registers DACR01—D/A Control Register 01 Bit : H'FFA6 D/A Converter 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE ⎯ ⎯ ⎯ ⎯ ⎯ Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/W R/W R/W ⎯ ⎯ ⎯ ⎯ ⎯ D/A Output Enable 0 0 Analog output DA0 is disabled 1 Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 Analog output DA1 is disabled 1 Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAO
Appendix B Internal I/O Registers PFCR2—Port Function Control Register 2 Bit : 7 6 ⎯ ⎯ H'FFAC 5 4 CS167E CS25E Ports 3 2 1 0 ASOD ⎯ ⎯ ⎯ Initial value : 0 0 1 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R R R AS Output Disable* Reserved Only 0 should be written to these bits 0 PF6 is designated as AS output pin 1 PF6 is designated as I/O port, and does not function as AS output pin Note: * This bit is valid in modes 4 to 6.
Appendix B Internal I/O Registers TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : H'FFB0 H'FFB1 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 1 1 0 1 0 Clock input disabled 1 Internal clock: counted at falling edge of φ/8 0 Internal clock: counted at falling edge of φ/64 1 Internal clock: co
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : Initial value : Read/Write : TCSR1 Bit : Initial value : Read/Write : H'FFB2 H'FFB3 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF ⎯ OS3 OS2 OS1 OS0 0 0 0 1 0 0 0 0 R/(W)* R/(W)* R/(W)* ⎯
Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA0 Bit TCORA1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCO
Appendix B Internal I/O Registers TCSR—Timer Control/Status Register Bit : Initial value : H'FFBC (W), H'FFBC (R) WDT 7 6 5 4 3 2 1 0 OVF WT/IT TME ⎯ ⎯ CKS2 CKS1 CKS0 0 Read/Write*1 : R/(W)*2 0 0 1 1 0 0 0 R/W R/W ⎯ ⎯ R/W R/W R/W Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 Clock Overflow period* (when φ = 20 MHz) 0 φ/2 25.6 μs 1 φ/64 819.2 μs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.4 ms 1 φ/131072 1.
Appendix B Internal I/O Registers TCNT—Timer Counter Bit : H'FFBC (W), H'FFBD (R) 7 6 5 4 3 WDT 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Note: The method for writing to TCNT different from that for general registers to prevent accidental overwritting. For details, see section 11.2.4, Notes on Register Access.
Appendix B Internal I/O Registers TSTR—Timer Start Register Bit : H'FFC0 TPU 7 6 5 4 3 2 1 0 ⎯ ⎯ CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ ⎯ R/W R/W R/W R/W R/W R/W Counter Start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'FFC8 Flash Memory (Valid in the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT only) Bit 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P : Initial value : 1/0* 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program* 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Note: * Valid for addresses H'000000 to H'03
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 Bit : H'FFC8 Flash Memory (Valid in the H8S/2319 F-ZTAT only) 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value : 1 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program 1* 0 Program mode cleared 1 Transition to program mode [Setting condition] When SWE1 = 1 and PSU1 = 1 Note: * Valid for addresses H'000000 to H'03FFFF.
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'FFC9 Flash Memory (Valid in H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT only) 7 6 5 4 3 2 1 0 FLER ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value : 0 0 0 0 0 0 0 0 Read/Write : R ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Bit : Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error ha
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 Bit : H'FFC9 Flash Memory (Valid in the H8S/2319 F-ZTAT only) 7 6 5 4 3 2 1 0 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program 2* 0 Program mode cleared 1 Transition to program mode [Setting condition] When SWE2 = 1 and PSU2 = 1 Erase 2* 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When SWE2 = 1 and E
Appendix B Internal I/O Registers EBR1—Erase Block Register 1 H'FFCA Flash Memory EBR2—Erase Block Register 2 H'FFCB Flash Memory (Valid only in the H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT) Bit : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W EBR1 7 6 5 4 3 2 1 0 EB15*3 EB14*3 EB13*2 EB12*2 EB11*1 EB10*1 EB9 EB8 Initial value : 0
Appendix B Internal I/O Registers FCCS—Flash Code Control Status Register Bit : H'FFC4 FLASH (Valid only in the H8S/2319C F-ZTAT) 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ FLER ⎯ ⎯ ⎯ SCO Initial value : 1 0 0 0 0 0 0 0 Read/Write : R R R R R R R (R)/W Source Program Copy Operation 0 Download of the on-chip programming/ erasing program to the on-chip RAM is not executed [Clearing condition] When download is completed 1 Request that the on-chip programming/ erasing program is downloaded
Appendix B Internal I/O Registers FPCS—Flash Program Code Select Register Bit : H'FFC5 FLASH (Valid only in the H8S/2319C F-ZTAT) 7 6 5 4 3 2 1 0 FVCHGE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Reserved bits These bits are always read as 0. The write value should always be 0.
Appendix B Internal I/O Registers FKEY—Flash Key Code Register Bit : H'FFC8 FLASH (Valid only in the H8S/2319C F-ZTAT) 7 6 5 4 3 2 1 0 K7 K6 K5 K4 K3 K2 K1 K0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Key Code H'A5 Writing to the SCO bit is enabled (The SCO bit cannot be set by the value other than H'A5.) H'5A Programming/erasing is enabled (The value other than H'5A is in software protection state.
Appendix B Internal I/O Registers FTDAR—Flash Transfer Destination Address Register H'FFCA FLASH (Valid only in the H8S/2319C F-ZTAT) Bit : 7 6 5 4 3 2 1 0 TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address TDA6 to TDA0 Description H'00 Download start address is set to H'FFBC00 H'01 Download start address is set to H'FFCC00 H'02 Download start address is set to H'FFDC00
Appendix B Internal I/O Registers TCR0—Timer Control Register 0 Bit : 7 6 5 CCLR2 CCLR1 CCLR0 H'FFD0 TPU0 (Valid only in the H8S/2319C F-ZTAT) 4 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input
Appendix B Internal I/O Registers TMDR0—Timer Mode Register 0 Bit : H'FFD1 TPU0 7 6 5 4 3 2 1 0 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ R/W R/W R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Notes: 1. MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR0H—Timer I/O Control Register 0H Bit : H'FFD2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU0 TGR0A I/O Control 0 0 0 1 1 0 1 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 1 0
Appendix B Internal I/O Registers TIOR0L—Timer I/O Control Register 0L Bit H'FFD3 : 7 6 5 4 3 2 1 0 : IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU0 TGR0C I/O Control 0 0 0 0 1 1 0 TGR0C Output disabled is output compare Initial output is register 0 output *1 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 × × × 1 output at compare match Toggle output at
Appendix B Internal I/O Registers TIER0—Timer Interrupt Enable Register 0 Bit : H'FFD4 TPU0 7 6 5 4 3 2 1 0 TTGE ⎯ ⎯ TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ ⎯ R/W R/W R/W R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled TGR Inter
Appendix B Internal I/O Registers TSR0—Timer Status Register 0 Bit : Initial value : Read/Write : H'FFD5 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA 1 1 0 0 0 0 0 0 ⎯ ⎯ ⎯ R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TPU0 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning a
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 Bit H'FFD6 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit H'FFD8 H'FFDA H'FFDC H'FFDE TPU0 TPU0 TPU0 TPU0 : 15 14 13 12 11 10 9 8 7 6 5
Appendix B Internal I/O Registers TCR1—Timer Control Register 1 Bit : 7 6 5 ⎯ CCLR1 CCLR0 H'FFE0 4 3 CKEG1 CKEG0 TPU1 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : ⎯ R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin in
Appendix B Internal I/O Registers TMDR1—Timer Mode Register 1 Bit : H'FFE1 TPU1 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR1—Timer I/O Control Register 1 Bit : H'FFE2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 TGR1A Output disabled is output compare Initial output is register 0 output 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare
Appendix B Internal I/O Registers TIER1—Timer Interrupt Enable Register 1 Bit : H'FFE4 TPU1 7 6 5 4 3 2 1 0 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ R/W R/W ⎯ ⎯ R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR1—Timer Status Register 1 Bit : Initial value : Read/Write : H'FFE5 7 6 5 4 3 2 1 0 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA 1 1 0 0 0 0 0 0 R ⎯ R/(W)* R/(W)* ⎯ ⎯ R/(W)* R/(W)* TPU1 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as out
Appendix B Internal I/O Registers TCNT1—Timer Counter 1 Bit H'FFE6 TPU1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers TCR2—Timer Control Register 2 Bit : H'FFF0 7 6 5 ⎯ CCLR1 CCLR0 Initial value : 0 0 0 0 Read/Write : ⎯ R/W R/W R/W 4 3 TPU2 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 R/W R/W R/W R/W CKEG1 CKEG0 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin i
Appendix B Internal I/O Registers TMDR2—Timer Mode Register 2 Bit : H'FFF1 TPU2 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ × : Don't care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR2—Timer I/O Control Register 2 Bit : H'FFF2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TPU2 TGR2A I/O Control 0 0 0 1 0 TGR2A is output 1 compare 0 register Output disabled Initial output is 0 output 1 1 0 1 × 0 1 1 output at compare match Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0
Appendix B Internal I/O Registers TIER2—Timer Interrupt Enable Register 2 Bit : H'FFF4 TPU2 7 6 5 4 3 2 1 0 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W ⎯ R/W R/W ⎯ ⎯ R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR2—Timer Status Register 2 Bit : Initial value : Read/Write : H'FFF5 7 6 5 4 3 2 1 0 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA 1 1 0 0 0 0 0 0 R ⎯ R/(W)* R/(W)* ⎯ ⎯ R/(W)* R/(W)* TPU2 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as out
Appendix B Internal I/O Registers TCNT2—Timer Counter 2 Bit H'FFF6 TPU2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 WDDR1 Reset R Q D P1nDR C P1n Internal address bus R Q D P1nDDR C Internal data bus Reset WDR1 Modes 4 to 6 Bus controller AmE bit TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 AmE: Address m enable Notes: n = 0 or 1 m = 20 or 21 Figure C.
Appendix C I/O Port Block Diagrams WDDR1 Reset R Q D P1nDR C P1n Internal address bus R Q D P1nDDR C Internal data bus Reset WDR1 Modes 4 to 6 RDR1 Bus controller AmE bit TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 AmE: Address m enable Notes: n = 2 or 3 m = 22 or 23 Figure C.
Appendix C I/O Port Block Diagrams R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n Internal data bus Reset WDR1 RDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 Note: n = 4 or 6 Figure C.1(c) Port 1 Block Diagram (Pins P14 and P16) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n Internal data bus Reset WDR1 RDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 Note: n = 5 or 7 Figure C.1(d) Port 1 Block Diagram (Pins P15 and P17) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams C.2 Port 2 R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n Internal data bus Reset WDR2 RDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR2 Input capture input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 Note: n = 0 to 7 Figure C.2 Port 2 Block Diagram (Pins P20 to P27) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams C.3 Port 3 R Q D P3nDDR C WDDR3 *1 Reset Internal data bus Reset R Q D P3nDR C P3n WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 RPOR3 Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal Figure C.3(a) Port 3 Block Diagram (Pins P30 and P31) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D P3nDDR C *1 WDDR3 Reset R Q D P3nDR C P3n *2 Internal data bus Reset WDR3 Reset R Q D P3nODR C WODR3 RODR3 RDR3 SCI module Serial receive data enable RPOR3 Serial receive data Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal Figure C.3(b) Port 3 Block Diagram (Pins P32 and P33) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D P3nDDR C *1 WDDR3 Reset R Q D P3nDR C P3n Internal data bus Reset WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Serial clock input Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR Notes: n = 4 or 5 1. Output enable signal 2.
Appendix C I/O Port Block Diagrams Port 4 RPOR4 P4n Internal data bus C.4 A/D converter module Analog input Legend: RPOR4: Read port 4 Note: n = 0 to 5 RPOR4 P4n Internal data bus Figure C.4(a) Port 4 Block Diagram (Pins P40 to P45) A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4: Read port 4 Note: n = 6 or 7 Figure C.4(b) Port 4 Block Diagram (Pins P46 and P47) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Port A Reset R Q D PAnPCR C WPCRA RPCRA Reset Modes 4 and 5 WDDRA *1 Reset Mode 7 Modes 4 to 6 PAn R Q D PAnDDR C R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: n = 0 to 3 1. Output enable signal 2. Open drain control signal Figure C.
Appendix C I/O Port Block Diagrams Port B Reset R Q D PBnPCR C WPCRB RPCRB Internal address bus Modes 6 and 7 Internal data bus C.6 Reset Modes 4 and 5 R Q D PBnDDR C WDDRB Reset PBn Mode 7 Modes 4 to 6 R Q D PBnDR C WDRB RDRB RPORB Legend: WDDRB: Write to PBDDR WDRB: Write to PBDR WPCRB: Write to PBPCR RDRB: Read PBDR RPORB: Read port B RPCRB: Read PBPCR Note: n = 0 to 7 Figure C.6 Port B Block Diagram (Pins PB0 to PB7) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Port C Reset R Q D PCnPCR C WPCRC RPCRC Reset Modes 4 and 5 R Q D PCnDDR C WDDRC Reset PCn Mode 7 Modes 4 to 6 R Q D PCnDR C WDRC RDRC RPORC Legend: WDDRC: Write to PCDDR WDRC: Write to PCDR WPCRC: Write to PCPCR RDRC: Read PCDR RPORC: Read port C RPCRC: Read PCPCR Note: n = 0 to 7 Figure C.7 Port C Block Diagram (Pins PC0 to PC7) Rev.7.00 Feb. 14, 2007 page 1080 of 1108 REJ09B0089-0700 Internal address bus Modes 6 and 7 Internal data bus C.
Appendix C I/O Port Block Diagrams Port D R Q D PDnPCR C WPCRD RPCRD Internal lower data bus Reset Internal upper data bus C.
Appendix C I/O Port Block Diagrams Reset R Q D PEnPCR C WPCRE RPCRE Mode 7 Internal lower data bus Port E Internal upper data bus C.9 Bus controller 8-bit bus mode Reset External address write R Q D PEnDDR C WDDRE Modes 4 to 6 PEn Modes 4 to 6 Reset R Q D PEnDR C WDRE RDRE RPORE Legend: WDDRE: Write to PEDDR WDRE: Write to PEDR WPCRE: Write to PEPCR RDRE: Read PEDR RPORE: Read port E RPCRE: Read PEPCR Note: n = 0 to 7 External address lower read Figure C.
Appendix C I/O Port Block Diagrams Port F Reset R Q D PF0DDR C Internal data bus C.10 WDDRF Modes 4 to 6 Reset Port CS25E bit PF0CS4S bit Bus controller BRLE bit R Q D PF0DR C PF0 WDRF Chip select RDRF RPORF Bus request input Legend: WDDRF: WDRF: RDRF: RPORF: CS25E: PF0CS4S: BRLE: Interrupt controller Write to PFDDR Write to PFDR Read PFDR Read port F CS25 enable Port F0 chip select 4 select Bus release enable IRQ interrupt input Figure C.10(a) Port F Block Diagram (Pin PF0) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D PF1DDR C WDDRF Reset R Q D PF1DR C PF1 Internal data bus Reset WDRF Modes 4 to 6 RDRF Bus controller BRLE bit Bus request acknowledge output Chip select RPORF Legend: WDDRF: WDRF: RDRF: RPORF: CS25E: PF1CS5S: BRLE: Write to PFDDR Write to PFDR Read PFDR Read port F CS25 enable Port F1 chip select 5 select Bus release enable Figure C.10(b) Port F Block Diagram (Pin PF1) Rev.7.00 Feb.
Reset R Q D PF2DDR C WDDRF Internal data bus Appendix C I/O Port Block Diagrams Bus controller Reset PF2 Modes 4 to 6 R Q D PF2DR C WDRF Wait enable Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input Legend: WDDRF: WDRF: RDRF: RPORF: Interrupt controller Write to PFDDR Write to PFDR Read PFDR Read port F IRQ Interupt input Figure C.10(c) Port F Block Diagram (Pin PF2) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF3DDR C WDDRF Mode 7 PF3 Modes 4 to 6 Reset R Q D PF3DR C Internal data bus Reset WDRF LWROD bit Bus controller LWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: LWROD: Write to PFDDR Write to PFDR Read PFDR Read port F LWR output disable Figure C.10(d) Port F Block Diagram (Pin PF3) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF4DDR C WDDRF Mode 7 PF4 Modes 4 to 6 Reset R Q D PF4DR C Internal data bus Reset WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.10(e) Port F Block Diagram (Pin PF4) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF5DDR C WDDRF Mode 7 PF5 Modes 4 to 6 Reset R Q D PF5DR C Internal data bus Reset WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.10(f) Port F Block Diagram (Pin PF5) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Modes 4 to 6 Mode 7 PF6 Modes 4 to 6 R Q D PF6DDR C WDDRF Reset Internal data bus Reset R D Q PF6DR C WDRF ASOD bit Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: ASOD: Write to PFDDR Write to PFDR Read PFDR Read port F AS output disable Figure C.10(g) Port F Block Diagram (Pin PF6) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Reset Modes 4 to 6 S R Q D D PF7DDR C WDDRF Reset R Q D PF7DR C PF7 Internal data bus Mode 7 WDRF φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.10(h) Port F Block Diagram (Pin PF7) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams C.11 Port G R Q D PG0DDR C WDDRG Reset Internal data bus Reset R Q D PG0DR C PG0 WDRG RDRG RPORG A/D convereter Legend: WDDRG: WDRG: RDRG: RPORG: A/D converter external trigger input Write to PGDDR Write to PGDR Read PGDR Read port G Interrput controller IRQ interrupt input Figure C.11(a) Port G Block Diagram (Pin PG0) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D PG1DDR C WDDRG Mode 7 PG1 Modes 4 to 6 Reset R Q D PG1DR C WDRG Internal data bus Reset Port CS167E bit CSS36 bit CS25E bit Bus controller Chip select 3 Chip select 6 RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS25E: CS167E: CSS36: Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable CS167 enable CS36 select Figure C.11(b) Port G Block Diagram (Pin PG1) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D PG2DDR C WDDRG Mode 7 PG2 Modes 4 to 6 Reset R Q D PG2DR C WDRG Internal data bus Reset Port CS25E bit Bus controller Chip select 2 RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS25E: Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable Figure C.11(c) Port G Block Diagram (Pin PG2) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams R Q D PG3DDR C WDDRG Mode 7 PG3 Modes 4 to 6 Reset R Q D PG3DR C Internal data bus Reset WDRG Port CS167E bit CSS17 bit Bus controller Chip select 1 Chip select 7 RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS167E: CSS17: Write to PGDDR Write to PGDR Read PGDR Read port G CS167 enable CS17 select Figure C.11(d) Port G Block Diagram (Pin PG3) Rev.7.00 Feb.
Appendix C I/O Port Block Diagrams Modes 4 and 5 Modes 6 and 7 S R D Q PG4DDR C WDDRG Mode 7 PG4 Modes 4 to 6 Reset Internal data bus Reset R Q D PG4DR C WDRG Bus controller Chip select 0 RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.11(e) Port G Block Diagram (Pin PG4) Rev.7.00 Feb.
Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.
Appendix D Pin States MCU Port Name Operating Pin Name Mode PA3/A19 4, 5 Reset Hardware Standby Mode L T PA2/A18 Software Standby Mode Bus-Released State Program Execution State Sleep Mode [OPE = 0] T T Address output T [DDR = 0] Input port [OPE = 1] kept PA1/A17 PA0/A16 6 T T [DDR · OPE = 0] T [DDR · OPE = 1] kept Port B [DDR = 1] Address output 7 T T kept kept I/O port 4, 5 L T [OPE = 0] T T Address output T [DDR = 0] Input port [OPE = 1] kept 6 T T [DDR · OPE = 0] T
Appendix D Pin States MCU Port Name Operating Pin Name Mode PF7 /φ 4 to 6 7 PF6/AS 4 to 6 Reset Hardware Standby Software Mode Standby Mode Clock T output T H T T Bus-Released State Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 0] Input port [DDR = 0] Input port [DDR = 1] H [DDR = 1] Clock output [DDR = 1] Clock output [DDR = 0] Input port [DDR = 0] Input port [DDR = 0] Input port [DDR = 1] H [DDR = 1] Clock output [DDR = 1] Clock output [ASOD = 1] kept [ASOD = 1]
Appendix D Pin States MCU Port Name Operating Pin Name Mode PF1/BACK/ 4 to 6 IRQ1/CS5 Reset Hardware Standby Mode T T Software Standby Mode Bus-Released State [BRLE + CS25E · PF1CS5S = 0] kept L [BRLE · DDR · CS25E · PF1CS5S =1] Program Execution State Sleep Mode [BRLE + CS25E · PF1CS5S = 0] I/O port [BRLE · DDR · CS25E · PF1CS5S =1] CS5 And [BRLE = 1] BACK [OPE = 0] T [BRLE · DDR · CS25E · PF1CS5S = 1] And [OPE = 1] H [BRLE = 1] BACK 7 PF0/BREQ/ 4 to 6 IRQ0/CS4 T T kept kept I/O port T
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode PG4/CS0 4, 5 H T 6 T 7 T T kept kept I/O port 4 to 6 T T [CS167E = 0] kept [CS167E = 0] kept [CS167E = 0] I/O port PG3/CS1/ CS7 PG2/CS2 Software Standby Mode Bus-Released State [DDR · OPE = 0] T T [DDR · OPE = 1] H Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] CS0 [CS167E · DDR = 1] [CS167E = 1] T T [CS167E · DDR = 1] Input port [CS167E · DDR · OPE = 1] T [CS167E · CSS1
Appendix D Pin States Port Name Pin Name PG1/CS3/ CS6/IRQ7 MCU Operating Mode Reset Hardware Standby Mode 4 to 6 T T Software Standby Mode Bus-Released State Program Execution State Sleep Mode [CSS36 · CS25E + CSS36 · CS167E = 0] kept [CSS36 · CS25E + CSS36 · CS167E = 0] kept [CSS36 · CS25E + CSS36 · CS167E = 0] I/O port [CSS36 · CS25E · DDR = 1] T [CSS36 · CS25E + CSS36 · CS167E = 1] T [CSS36 · CS25E · DDR = 1] Input port [CSS36 · CS167E · DDR = 1] T [CSS36 · CS167E · DDR = 1] Input port
Appendix D Pin States CSS36: CSS17: PF1CS5S: PF0CS4S: LWROD: DAOEn: CS36 select CS17 select Port F1 chip select 5 select Port F0 chip select 4 select LWR output disable D/A output enable n (n = 0, 1) Notes: 1. The WDTOVF pin function is not usable on the F-ZTAT version. 2. A low level is output if a WDT overflow occurs while WT/IT is set to 1. Rev.7.00 Feb.
Appendix E Product Lineup Appendix E Product Lineup Table E.1 H8S/2319 Group Product Lineup Product Type H8S/2319 Part No.
Appendix E Product Lineup Product Type H8S/2314 Part No. Mask ROM version HD6432314 F-ZTAT version HD64F2314 Marking Package (Package Code) HD6432314VTE 100-pin TQFP (TFP-100B) HD6432314VE 100-pin QFP (FP-100A) HD64F2314VTE 100-pin TQFP (TFP-100B) HD64F2314VF H8S/2312S ROMless version HD6412312S 100-pin QFP (FP-100A) HD6412312SVTE 100-pin TQFP (TFP-100B) HD6412312SVF 100-pin QFP (FP-100A) Notes: 1. The on-chip debug function can be used with the E10A emulator (E10A compatible version). 2.
Appendix F Package Dimensions Appendix F Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51 76 50 bp Reference Symbol Nom Max 14 D c c1 HE Dimension in Millimeters Min E 14 A2 1.00 *2 E b1 Terminal cross section HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A1 0.00 0.10 0.
Appendix F Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code TFP-100G/TFP-100GV MASS[Typ.] 0.4g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51 76 50 Reference Symbol HE b1 c c1 *2 E bp Dimension in Millimeters Min 12 E 12 A2 26 Terminal cross section ZE 100 Nom D 1.00 HD 13.8 14.0 14.2 HE 13.8 14.0 14.2 A1 0.00 0.10 0.20 bp 0.13 0.18 0.
Appendix F Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JE-B Previous Code FP-100A/FP-100AV MASS[Typ.] 1.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 80 51 81 50 bp Reference Symbol c c1 HE *2 E b1 Dimension in Millimeters Min 20 14 ZE 31 100 HD 24.4 24.8 25.2 HE 18.4 18.8 19.2 A1 0.00 0.20 0.30 bp 0.24 0.32 0.40 3.10 A 1 30 θ A1 L L1 Detail F *3 y bp M x 0.
Appendix F Package Dimensions JEITA Package Code P-TFLGA113-8x8-0.65 RENESAS Code PTLG0113JA-A Previous Code TLP-113V MASS[Typ.] 0.12g D w S B E w S A x4 v y1 S A S y S e Z A D Reference Symbol Nom D 8.0 E 8.0 Max e L Dimension in Millimeters Min K J H B G F v 0.15 w 0.20 A 1.2 A1 E e D b 0.65 0.30 0.35 0.40 Z E C B A 1 2 3 4 5 6 7 φb 8 9 10 11 φ× M S A B Figure F.4 TLP-113V Package Dimensions Rev.7.00 Feb.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2319 Group Publication Date: 1st Edition, March 1999 Rev.7.00, February 14, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2319 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0089-0700
