Datasheet

Section 2 CPU
Rev.7.00 Feb. 14, 2007 page 64 of 1108
REJ09B0089-0700
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7 Exception Handling Types and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Trace End of instruction
execution or end of
exception-handling
sequence
*
1
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence.
Interrupt End of instruction
execution or end of
exception-handling
sequence
*
2
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence.
Low
Trap instruction When TRAPA instruction
is executed
Exception handling starts when
a trap (TRAPA) instruction is
executed
*
3
.
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not
executed at the end of the RTE instruction.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
3. Trap instruction exception handling is always accepted, in the program execution state.