Datasheet

Section 1 Overview
Rev.7.00 Feb. 14, 2007 page 1 of 1108
REJ09B0089-0700
Section 1 Overview
1.1 Overview
The H8S/2319 Group is a series of microcomputer (MCU: microcomputer unit), built around the
H8S/2000 CPU, employing Renesas's proprietary architecture, and equipped with supporting
functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting functions required for system configuration include data transfer controller
(DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), 8-bit timer, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
Single-power-supply flash memory (F-ZTAT™
*
) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications. ROM is connected to
the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
Instruction fetching is thus speeded up, and processing speed increased.
The features of the H8S/2319 Group are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.