Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 918 of 982
REJ09B0054-0600
(3) Bus Timing
Table 27.44 lists the bus timing.
Table 27.44 Bus Timing
Condition A (F-ZTAT version and masked ROM version):
V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V,
V
ref
= 2.7 V to AV
CC
, V
SS
=AV
SS
= 0 V,
φ = 2 to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B (F-ZTAT version): V
CC
= 2.2 V to 3.6 V, AV
CC
= 2.2 V to 3.6 V,
V
ref
= 2.2 V to AV
CC
, V
SS
=AV
SS
= 0 V,
φ = 2 to 6.25 MHz,
T
a
= –20°C to +75°C (regular specifications)
Condition C (Masked ROM version): V
CC
= 2.2 V to 3.6 V, AV
CC
= 2.2 V to 3.6 V,
V
ref
= 2.2 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 2 to 6.25 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition A Conditions B, C
Test
Item Symbol Min Max Min Max Unit Conditions
Address delay time t
AD
⎯ 50 ⎯ 90 ns
Address setup time t
AS
0.5 × t
cyc
−
30
⎯ 0.5 × t
cyc
− 60
⎯ ns
Address hold time t
AH
0.5 × t
cyc
−
15
⎯ 0.5 × t
cyc
− 30
⎯ ns
Figures 27.14
to 27.18
CS delay time t
CSD
⎯ 50 ⎯ 90 ns
AS delay time t
ASD
⎯ 50 ⎯ 90 ns
RD delay time 1 t
RSD1
⎯ 50 ⎯ 90 ns
RD delay time 2 t
RSD2
⎯ 50 ⎯ 90 ns
Read data setup time t
RDS
30 ⎯ 50 ⎯ ns
Read data hold time t
RDH
0 ⎯ 0 ⎯ ns
Read data access time 1 t
ACC1
⎯ 1.0 × t
cyc
− 65
⎯ 1.0 × t
cyc
− 90
ns