Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 902 of 982
REJ09B0054-0600
Conditions A, B
Item Symbol Min Max Unit Test Conditions
WDT1 BUZZ output delay time t
BUZD
⎯ 100 ns Figure 27.30
SCI
*
Asynchronous t
Scyc
4 ⎯ t
cyc
Figure 27.31
Input clock
cycle
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
⎯ 1.5 t
cyc
Input clock fall time t
SCKf
⎯ 1.5
Transmit data delay time t
TXD
⎯ 100 ns Figure 27.32
Receive data setup time
(synchronous)
t
RXS
75 ⎯ ns
Receive data hold time
(synchronous)
t
RXH
75 ⎯ ns
A/D
converter
Trigger input setup time t
TRGS
40 ⎯ ns Figure 27.33
Note: * The high level of P35/SCK1 and P34 is driven by NMOS. In order to output a high level
at V
CC
= 4.5 V or below, a pull-up resistance must be connected externally.