Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 897 of 982
REJ09B0054-0600
(1) Clock Timing
Table 27.30 lists the clock timing
Table 27.30 Clock Timing
Condition A (F-ZTAT version): V
CC
= 3.0 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B (Masked ROM version): V
CC
= 2.7 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Conditions A, B
Item Symbol Min Typ Max Unit
Test
Conditions
Clock cycle time t
cyc
74 ⎯ 500 ns
Clock high pulse width t
CH
25 ⎯ ⎯ ns
Clock low pulse width t
CL
25 ⎯ ⎯ ns
Clock rise time t
Cr
⎯ ⎯ 10 ns
Clock fall time t
Cf
⎯ ⎯ 10 ns
Figure 27.10
Reset oscillation stabilization
time (crystal)
t
OSC1
20 ⎯ ⎯ ms Figure 27.11
Software standby oscillation
stabilization time (crystal)
t
OSC2
8 ⎯ ⎯ ms
External clock output stabilization
delay time
t
DEXT
500 ⎯ ⎯ µs Figure 27.11
Subclock oscillation stabilization
time
t
OSC3
⎯ ⎯ 2 s
Subclock oscillator frequency f
SUB
⎯ 32.768 ⎯ kHz
Subclock (φ
SUB
) cycle time t
SUB
⎯ 30.5 ⎯ µs