Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 880 of 982
REJ09B0054-0600
(5) Timing of On-Chip Peripheral Modules
Table 27.21 lists the timing of on-chip peripheral modules. Table 27.22 lists the I
2
C bus timing.
Table 27.21 Timing of On-Chip Peripheral Modules
Condition A (F-ZTAT version and masked ROM version):
V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V,
V
ref
= 2.7 V to AV
CC
, V
SS
= AV
SS
= 0 V, φ = 32.768 kHz,
2 to 16.0 MHz, T
a
= –20°C to +75°C (regular specifications)
Condition B (Masked ROM version): V
CC
= 2.2 V to 3.6 V, AV
CC
= 2.2 V to 3.6 V,
V
ref
= 2.2 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 2 to 6.25 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition C (F-ZTAT version and masked ROM version):
V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V,
V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 10.0 MHz to 20.0 MHz,
T
a
= 20°C to +75°C (regular specifications),
T
a
= 40°C to +85°C (wide-range specifications)
Condition A
Condition B Condition C
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
I/O port
*
Output data delay
time
t
PWD
⎯ 70 ⎯ 150 ⎯ 50 ns Figure 27.24
Input data setup
time
t
PRS
50 ⎯ 80 ⎯ 30 ⎯
Input data hold time t
PRH
50 ⎯ 80 ⎯ 30 ⎯
TPU Timer output delay
time
t
TOCD
⎯ 70 ⎯ 150 ⎯ 50 ns Figure 27.25
Timer input setup
time
t
TICS
40 ⎯ 60 ⎯ 30 ⎯
Timer clock input
setup time
t
TCKS
40 ⎯ 60 ⎯ 30 ⎯ ns Figure 27.26
Timer clock
pulse width
Single
edge
t
TCKWH
1.5 ⎯ 1.5 ⎯ 1.5 ⎯ t
cyc
Both
edges
t
TCKWL
2.5 ⎯ 2.5 ⎯ 2.5 ⎯