Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 858 of 982
REJ09B0054-0600
Table 27.9 I
2
C Bus Timing
Conditions: V
CC
= 4.0 V to 5.5 V, V
SS
= 0 V, φ = 5 MHz to maximum operating frequency,
T
a
= –20°C to +75°C
Standard Value
Item Symbol Min Typ Max Unit Test Conditions
SCL input cycle time t
SCL
12 ⎯ ⎯ t
cyc
SCL input high pulse width t
SCLH
3 ⎯ ⎯ t
cyc
SCL input low pulse width t
SCLL
5 ⎯ ⎯ t
cyc
SCL, SDA input rise time t
Sr
⎯ ⎯ 7.5
*
t
cyc
SCL, SDA input fall time t
Sf
⎯ ⎯ 300 ns
SCL, SDA input spike pulse
elimination time
t
SP
⎯ ⎯ 1 t
cyc
SDA input bus free time t
BUF
5 ⎯ ⎯ t
cyc
Start condition input hold
time
t
STAH
3 ⎯ ⎯ t
cyc
Retransmission start
condition input setup time
t
STAS
3 ⎯ ⎯ t
cyc
Stop condition input setup
time
t
STOS
3 ⎯ ⎯ t
cyc
Data input setup time t
SDAS
0.5 ⎯ ⎯ t
cyc
Data input hold time t
SDAH
0 ⎯ ⎯ ns
Figure 27.7
SCL, SDA load capacitance C
b
⎯ ⎯ 400 pF
Note: * Can be 7.5 t
cyc
or 17.5 t
cyc
depending on the clock used in the I
2
C module. For details,
see section 16.6, Usage Notes.