Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 857 of 982
REJ09B0054-0600
(4) Timing of On-Chip Peripheral Modules
Table 27.8 lists the timing of on-chip peripheral modules.
Table 27.8 Timing of On-Chip Peripheral Modules
Condition A: V
CC
= 4.0 V to 5.5 V, AV
CC
= 4.0 V to 5.5 V, V
ref
= 4.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition A
Item Symbol Min Max Unit Test Conditions
Output data delay time t
PWD
⎯ 100 ns
Input data setup time t
PRS
50
⎯
I/O ports
Input data hold time t
PRH
50
⎯
Figure 27.24
TPU Timer output delay time t
TOCD
⎯ 100 ns
Timer input setup time t
TICS
40
⎯
Figure 27.25
Timer clock input setup time t
TCKS
40 ⎯ ns Figure 27.26
Single edge t
TCKWH
1.5 ⎯ t
cyc
Timer clock
pulse width
Both edges t
TCKWL
2.5 ⎯
TMR Timer output delay time t
TMOD
⎯ 100 ns Figure 27.27
Timer reset input setup time t
TMRS
50 ⎯ ns Figure 27.29
Timer clock input setup time t
TMCS
50 ⎯ ns Figure 27.28
Single edge t
TMCWH
1.5 ⎯ Timer clock
pulse width
Both edges t
TMCWL
2.5 ⎯
t
cyc
WDT1 BUZZ output delay time t
BUZD
⎯ 100 ns Figure 27.30
SCI Asynchronous t
Scyc
4 ⎯ t
cyc
Input clock
cycle
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
⎯ 1.5 t
cyc
Input clock fall time t
SCKf
⎯ 1.5
Figure 27.31
Transmit data delay time t
TXD
⎯ 100 ns
Receive data setup time
(synchronous)
t
RXS
75 ⎯ ns
Receive data hold time
(synchronous)
t
RXH
75 ⎯ ns
Figure 27.32
A/D
converter
Trigger input setup time t
TRGS
40 ⎯ ns Figure 27.33