Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 854 of 982
REJ09B0054-0600
(1) Clock Timing
Table 27.5 lists the clock timing.
Table 27.5 Clock Timing
Condition A: V
CC
= 4.0 V to 5.5 V, AV
CC
= 4.0 V to 5.5 V, V
ref
= 4.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition A
Item Symbol Min Max Unit Test Conditions
Clock cycle time t
cyc
74 100 ns
Clock high pulse width t
CH
25 ⎯ ns
Clock low pulse width t
CL
25 ⎯ ns
Clock rise time t
Cr
⎯ 10 ns
Clock fall time t
Cf
⎯ 10 ns
Figure 27.10
Oscillation stabilization time at
reset (crystal)
t
OSC1
20 ⎯ ms Figure 27.11
Oscillation stabilization time in
software standby (crystal)
t
OSC2
8 ⎯ ms
External clock output stabilization
delay time
t
DEXT
500 ⎯ µs Figure 27.11
32-kHz clock oscillation
stabilization time
t
OSC3
⎯ 2 s
Subclock oscillator frequency f
SUB
32.768 32.768 kHz
Subclock (φ
SUB
) cycle time t
SUB
30.5 30.5 µs