Datasheet

Section 26 List of Registers
Rev. 6.00 Mar. 18, 2010 Page 807 of 982
REJ09B0054-0600
Section 26 List of Registers
This section gives information on the on-chip I/O registers and is configured as described below.
1. Register Addresses (In Address Order)
⎯ Descriptions by functional module, in ascending order of addresses
⎯ Descriptions by functional module
⎯ The number of access states are given
2. Register Bits
⎯ Bit configurations of the registers are described in the same order as the Register Addresses
(In Address Order)
⎯ Reserved bits are indicated by “⎯” in the bit name
⎯ A blank in the bit name indicates that the corresponding whole register is allocated to the
counter or data
3. Register States in Each Operating Mode
⎯ Register states are described in the same order as the Register Addresses (In Address
Order)
⎯ The register states described are for the basic operating modes. If there is a specific reset
for an on-chip module, refer to the section on that on-chip module
26.1 Register Addresses (In Address Order)
The data bus width indicates the number of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.