Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 801 of 982
REJ09B0054-0600
24.12 Usage Notes
24.12.1 I/O Port Status
In software standby mode and watch mode, I/O port states are retained. Therefore, there is no
reduction in current dissipation for the output current when a high-level signal is output.
24.12.2 Current Dissipation during Oscillation Settling Wait Period
Current dissipation increases during the oscillation settling wait period.
24.12.3 DTC and DMAC* Module Stop
Depending on the operating status of the DTC and DMAC*, the MSTPA6 bit and MSTPA7 bit
may not be set to 1. Setting of the DTC and DMAC* module stop mode should be carried out only
when the respective module is not activated.
For details, refer to section 8, DMA Controller (DMAC) and section 9, Data Transfer Controller
(DTC).
Note: * Supported only by the H8S/2239 Group.
24.12.4 On-Chip Peripheral Module Interrupt
• Module Stop Mode
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if
module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC
*
1
or DTC activation source. Interrupts should
therefore be disabled before entering module stop mode.
• Subactive Mode/Watch Mode
On-chip peripheral modules (DMAC
*
1
, DTC, TPU, IIC
*
2
) that stop operation in subactive
mode cannot clear interrupts in subactive mode. Therefore, if subactive mode is entered when
an interrupt is requested, CPU interrupt factors cannot be cleared.
Interrupts should therefore before executing the SLEEP instruction and entering subactive or
watch mode.
Notes: 1. Supported only by the H8S/2239 Group.
2. Not available in the H8S/2237 Group and H8S/2227 Group.