Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 790 of 982
REJ09B0054-0600
• MSTPCRC
Bit Bit Name Initial Value R/W Target Module
7 MSTPC7 1 R/W Serial communication interface 3 (SCI_3)
6 MSTPC6
*
1
1 R/W
5 MSTPC5 1 R/W D/A converter
*
4
4 MSTPC4 1 R/W PC break controller (PBC)
3 MSTPC3 1 R/W IEBus controller (IEB)
*
5
2 MSTPC2
*
1
1 R/W
1 MSTPC1
*
1
1 R/W
0 MSTPC0
*
1
1 R/W
Notes: 1. Bits MSTPA3, MSTPA2, MSTPB5, MSTPB2 to MSTPB0, MSTPC6, MSTPC2 to
MSTPC0 are readable/writable. The initial value of them is 1. The write value should
always be 1.
2. Supported only by the H8S/2239 Group.
3. Not available in the H8S/2237 Group and H8S/2227 Group.
4. Not available in the H8S/2227 Group.
5. Supported only by the H8S/2258 Group.
24.2 Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (DMAC* and DTC) also operate in medium-speed
mode.
On-chip peripheral modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in
LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an
interrupt, medium-speed mode is restored.