Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 776 of 982
REJ09B0054-0600
Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (3)
(H8S/2238R, H8S/2236R)
F-ZTAT
F-ZTAT and
Masked ROM
V
CC
= 2.7 V to 3.6 V V
CC
= 2.2 V to 3.6 V
Item Symbol Min Max Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
37 — 80 — ns
External clock input
high pulse width
t
EXH
37 — 80 — ns
External clock rise
time
t
EXr
7 — 15 ns
Figure 23.5
External clock fall
time
t
EXf
— 7 — 15 ns
Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to
match the input waveform.
(Example: If t
EXL
= t
EXH
= 37 ns and t
EXr
= t
EXf
= 7 ns, the clock cycle = 88 ns and the maximum
operating frequency = 11.3 MHz)
Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (4)
(H8S/2237 Group, H8S/2227 Group)
F-ZTAT and
Masked ROM Masked ROM ZTAT
V
CC
=
2.7 V to 3.6 V
V
CC
=
2.2 V to 3.6 V
V
CC
=
2.7 V to 3.6 V
Item Symbol Min Max Min Max Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
37 — 80 — 50 — ns
External clock input
high pulse width
t
EXH
37 — 80 — 50 — ns
External clock rise
time
t
EXr
— 7 — 15 — 10 ns
Figure 23.5
External clock fall
time
t
EXf
— 7 — 15 — 10 ns
Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to
match the input waveform.
(Example: If t
EXL
= t
EXH
= 37 ns and t
EXr
= t
EXf
= 7 ns, the clock cycle = 88 ns and the maximum
operating frequency = 11.3 MHz)