Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 775 of 982
REJ09B0054-0600
Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (1)
(H8S/2258 Group)
V
CC
= 4.0 V to 5.5 V
Item Symbol Min Max Unit Test Conditions
External clock input low
pulse width
t
EXL
37 — ns
External clock input high
pulse width
t
EXH
37 — ns
External clock rise time t
EXr
— 7 ns
Figure 23.5
External clock fall time t
EXf
— 7 ns
Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to
match the input waveform.
(Example: If t
EXL
= t
EXH
= 37 ns and t
EXr
= t
EXf
= 7 ns, the clock cycle = 88 ns and the maximum
operating frequency = 11.3 MHz)
Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (2)
(H8S/2238B, H8S/2236B)
F-ZTAT
Masked ROM
V
CC
= 3.0 V to 5.5 V V
CC
= 2.7 V to 5.5 V
Item Symbol Min Max Min Max Unit
Test
Conditions
External clock input
low pulse width
t
EXL
37 — 37 — ns
External clock input
high pulse width
t
EXH
37 — 37 — ns
External clock rise
time
t
EXr
— 7 — 7 ns
Figure 23.5
External clock fall
time
t
EXf
— 7 — 7 ns
Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to
match the input waveform.
(Example: If t
EXL
= t
EXH
= 37 ns and t
EXr
= t
EXf
= 7 ns, the clock cycle = 88 ns and the maximum
operating frequency = 11.3 MHz)