Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 770 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
1
0
STC1
STC0
0
0
R/W
R/W
Multiplication factor setting
Specifies multiplication factor of the PLL circuit built
in the evaluation chip. The specified multiplication
factor becomes valid software standby mode, watch
mode, or subactive mode is entered.
These bits should be set to 11 in this LSI. Since the
value becomes STC1 = STC0 = 0 after a reset, set
STC1 = STC0 = 1.
00: × 1
01: × 2 (setting prohibited)
10: × 4 (setting prohibited)
11: PLL is bypass
Note: * When watch mode or subactive mode is entered, set high-speed mode.
23.2 System Clock Oscillator
System clock pulses can be supplied by connecting a crystal resonator, or by input of an external
clock.
23.2.1 Connecting a Crystal Resonator
A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping
resistance R
d
according to table 23.1. An AT-cut parallel-resonance crystal should be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Note: C
L1
and C
L2
are reference values including the floating capacitance of the board.
Figure 23.2 Connection of Crystal Resonator (Example)