Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 769 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
This bit selects the sampling frequency of the
subclock (φ
SUB
) generated by the subclock oscillator
is sampled by the clock (φ) generated by the system
clock oscillator
Set 0 when φ is 5 MHz or higher. Set 1 when φ is 2.1
MHz or lower. Any value can be set when φ is 2.1 to
5 MHz.
0: Sampling using 1/32 × φ
1: Sampling using 1/4 × φ
4 SUBSTP 0 R/W Subclock Enable
This bit enables/disables subclock generation. This
bit should be set to 1 when subclock is not used.
0: Enables subclock generation.
1: Disables subclock generation.
3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control Bit
Selects whether or not built-in feedback resistance
and duty adjustment circuit of the system clock
generator are used when an external clock is input.
Do not access when the crystal resonator is used.
After setting this bit in the external clock input state,
enter software standby mode, watch mode, or
subactive mode. When software standby mode,
watch mode, or subactive mode is entered, switch
whether or not built-in feedback resistance and duty
adjustment circuit are used.
0: Built-in feedback resistance and duty adjustment
circuit of the system clock generator used.
1: Built-in feedback resistance and duty adjustment
circuit of the system clock generator not used.
2 — 0 R/W Reserved
This bit is readable/writable, but the write value
should always be 0.