Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 768 of 982
REJ09B0054-0600
23.1.2 Low-Power Control Register (LPWRCR)
LPWRCR performs down-mode control, selects sampling frequency for eliminating noise,
performs subclock generation control, and specifies multiplication factor.
Bit Bit Name Initial Value R/W Description
7 DTON 0 R/W Direct Transfer ON Flag
0: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation
shifts to sleep mode, software standby mode, or
watch mode
*
.
When the SLEEP instruction is executed in sub-
active mode, operation shifts to sub-sleep mode
or watch mode.
1: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation
shifts directly to sub-active mode
*
, or shifts to
sleep mode or software standby mode.
When the SLEEP instruction is executed in sub-
active mode, operation shifts directly to high-
speed mode, or shifts to sub-sleep mode.
6 LSON 0 R/W Low Speed ON Fag
0: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation
shifts to sleep mode, software standby mode, or
watch mode
*
.
When the SLEEP instruction is executed in sub-
active mode, operation shifts to watch mode
*
or
shifts directly to high-speed mode.
Operation shifts to high-speed mode when watch
mode is cancelled.
1: When the SLEEP instruction is executed in high-
speed mode, operation shifts to watch mode or
sub-active mode.
When the SLEEP instruction is executed in sub-
active mode, operation shifts to sub-sleep mode
or watch mode.
Operation shifts to sub-active mode when watch
mode is cancelled.