Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 766 of 982
REJ09B0054-0600
23.1 Register Descriptions
The on-chip clock pulse generator has the following registers.
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
23.1.1 System Clock Control Register (SCKCR)
SCKCR performs medium-speed mode control.
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W φ Clock Output Prohibited
Controls φ output.
• High-speed mode, medium-speed mode,
subactive mode, sleep mode, and subsleep
mode
0: φ output
1: Fixed to high
• Software standby mode, watch mode, and direct
transition
0: Fixed to high
1: Fixed to high
• Hardware standby mode
0: High impedance
1: High impedance
6 — 0 R/W Reserved
This bit is readable/writable, but the write value
should always be 0.
5, 4 — All 0 — Reserved
These bits are always read as 0, and cannot be
modified.
3 — 0 R/W Reserved
This bit is readable/writable, but the write value
should always be 0.