Datasheet

Section 20 Flash Memory (F-ZTAT Version)
Rev. 6.00 Mar. 18, 2010 Page 740 of 982
REJ09B0054-0600
20.8.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.12 should be
followed.
1. Prewriting (setting erase block data to all 0) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in
turn.
3. The time during which the E1 bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (t
sesu
+ t
se
+ t
ce
+ t
cesu
) ms as the WDT overflow period.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
are B'0. Verify data can be read in words from the address to which a dummy write was
performed.
5. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is (N).