Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 704 of 982
REJ09B0054-0600
17.8 Usage Notes
17.8.1 Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing module stop mode. For details, refer to section 24, Power-Down Modes.
17.8.2 Permissible Signal Source Impedance
This LSI’s analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided externally, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/μs or greater) (see figure 17.9). When converting a high-speed
analog signal, a low-impedance buffer should be inserted.
17.8.3 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i.e., acting as antennas).
A/D converter
equivalent circuit
This LSI
20 pF
C
in
=
15 pF
10 k Ω
Low-pass
filter C
to 0.1 μF
Sensor output
impedance
to 5 k
Ω
Sensor input
Figure 17.9 Example of Analog Input Circuit