Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 701 of 982
REJ09B0054-0600
17.5.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 17.6 shows the
timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 17.6 External Trigger Input Timing
17.6 Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1
after A/D conversion is completed. The DMAC* and the DTC can be activated by an ADI
interrupt. Having the converted data read by the DMAC* or the DTC in response to an ADI
interrupt enables continuous conversion without imposing a load on software.
Note: * Supported only by the H8S/2239 Group.
Table 17.5 A/D Converter Interrupt Source
Name Interrupt Source Interrupt Source Flag
DTC
Activation
DMAC*
Activation
ADI A/D conversion completed ADF Possible Possible
Note: * Supported only by the H8S/2239 Group.