Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 696 of 982
REJ09B0054-0600
17.4 Interface to Bus Master
ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus
master accesses to the upper byte of the registers directly while to the lower byte of the registers
via the temporary register (TEMP).
Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data
will be transferred to the CPU and the lower-byte data will be transferred to TEMP. Then, when
the lower-byte data is read, the lower-byte data will be transferred to the CPU.
When data in ADDR is read, the data should be read from the upper byte and lower byte in the
order. When only the upper-byte data is read, the data is guaranteed. However, when only the
lower-byte data is read, the data is not guaranteed.
Figure 17.2 shows data flow when accessing to ADDR.
TEMP
(H'40)
ADDRnL
(H'40)
ADDRnH
(H'AA)
TEMP
(H'40)
ADDRnL
(H'40)
ADDRnH
(H'AA)
Read the upper byte
Read the lower byte
(n = A to D)
(n = A to D)
Module data bus
Module data bus
Bus interface
Bus interface
Bus master
(H'40)
Bus master
(H'AA)
Figure 17.2 Access to ADDR (When Reading H'AA40)