Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 690 of 982
REJ09B0054-0600
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
Off during A/D conversion
wait time, on during A/D
conversion.
+
Sample-and-
hold circuit
ADI
interrupt
Bus interface
Successive approximations
register
Multiplexer
ADCSR
ADCR
ADDRD ADDRC
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Legend:
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
ADTRG
Conversion start
trigger from TPU or 8-bit timer
φ /2
φ /4
φ /8
φ /16
AV
CC
AV
SS
Vref
ADDRA ADDRB
Figure 17.1 Block Diagram of A/D Converter