Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 686 of 982
REJ09B0054-0600
SASLA R/W
SASLA
R/W ADATA2
SASLA
R/W ASLA R/W
A
DATA3
A
DATA4
DATA1
I
2
C bus interface
(Master transmit mode)
Transmit data match
Transmit timing match
• Receive address is ignored • Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I
2
C bus interface operates
as a slave device.
• Arbitration is lost
• The AL flag in ICSR is set to 1
Transmit data does not match
Other device
(Master transmit mode)
I
2
C bus interface
(Slave receive mode)
Data contention
Figure 16.27 Diagram of Erroneous Operation Wen Arbitration Is Lost
Though it is prohibited in the normal I
2
C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(1) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(2) Set the MST bit to 1.
(3) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
16. Note on Wait Operation in Master Mode
When the interrupt request flag (IRIC) is cleared from 1 to 0 between the falling edge of the
7th clock and the falling edge of the 8th clock in master mode using the wait function, a wait
may not be inserted after the falling edge of the 8th clock and 9th clock pulse may be output
continuously.
When using the wait operation, note the following to clear the IRIC flag.
After the IRIC flag is set to 1 at the rising edge of the 9th clock, clear the IRIC falg before the
rising edge of the 7th clock (when the value of the BC2 to BC0 counter is 2 or more).
If the clearing of the IRIC flag is deleyed due to interrupt handling etc. and the value of the BC
counter reaches 1 or 0, confirm that the SCL pin is low and then clear the IRIC flag after the
BC2 to BC0 counter reaches 0 (see figure 16.28).