Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 682 of 982
REJ09B0054-0600
9. Notes on I
2
C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
Stop condition
SCL
IRIC
[1] Determination of SCL = low
9th clock
VIH
High period secured
[2] Stop condition instruction issuance
SDA
As waveform rise is late,
SCL is detected as low
Figure 16.23 Timing of Stop Condition Issuance
10. Notes on IRIC Flag Clearance when Using Wait Function
If the SCL rise time exceeds the designated duration or if the slave device is of the type that
keeps SCL low and applies a wait state when the wait function is used in the master mode of
the I
2
C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone
low, as shown below.
Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can
cause the SDA value to change before SCL goes low, resulting in a start condition or stop
condition being generated erroneously.
SCL
SCL = high duration
maintained
[1] Judgement that SCL = low [2] IRIC clearance
V
IH
SDA
IRIC
SCL = low detected
Figure 16.24 IRIC Flag Clearance in WAIT = 1 Status