Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 676 of 982
REJ09B0054-0600
16.5 Interrupt Source
IICI is the interrupt source of IIC. Table 16.6 shows each interrupt source and its priority. The
ICCR interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt
controller.
Table 16.6 IIC Interrupt Source
Channel Name Enable Bit Interrupt Source
Interrupt
Flag
Interrupt
Priority
0 IICI0 IEIC I
2
C bus interface interrupt
request
IRIC High
1 IICI1 IEIC I
2
C bus interface interrupt
request
IRIC
Low
16.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
2
C bus, neither
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read PORT in each I
2
C bus
output pin, and check that SCL and SDA are both low. Even if the ICE bit is set to 1, it is
possible to monitor the pin state by reading the PORT register so long as the DDR I/O port
register corresponding to the pin has been cleared to 0. Then issue the instruction that
generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared
to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
3. Table 16.7 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.