Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 671 of 982
REJ09B0054-0600
6. Clear the IRIC flag to 0.
7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in
the ACKB bit to 0.
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SCL on the slave side.
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. At the
same time, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
To restart slave transmit mode operation, make the initial settings once again.
SDA
(master output)
SDA
(slave output)
21 21436587 998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRT
ICDRS
IRIC
TDRE
SCL
(master output)
SCL
(slave output)
Slave receive mode Slave transmit mode
[3] ICDR write
User processing
Data 1
Data 1 Data 2
Data 1 Data 2
Data 2
A
R/W
A
[3] IRIC clearance
[3] IRIC clearance
[5] IRIC clearance
[5] ICDR write
[2]
[4]
Figure 16.18 Example of Slave Transmit Mode Operation Timing (MLS = 0)