Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 664 of 982
REJ09B0054-0600
9821345678 9
A
A
Data 2 Data 3
Data 3Data 2Data 1
[3]
[3]
[8]
[12] [12]
Stop condition
generated
[4] IRTR = 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 0
1 clock cycle wait time
Bit 7
[4] IRTR = 1 [13] IRTR = 1[13] IRTR = 0
[15] WAIT cleared to 0
IRIC clearance
[14] IRIC clearance
[11] IRIC clearance
[6] IRIC clearance
User processing
[10] ICDR read (data 2)
[16] ICDR read (data 3)
[9] TRS set to 1
[7] ACKB set to 1
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
[17] Stop condition
issued
Figure 16.13 Example of Master Receive Mode Stop Condition Generation Timing
(MLS = ACKB = 0, WAIT = 1)
16.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal.
The slave device compares its own address with the slave address in the first frame following the
establishment of the start condition issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master device.
Figure 16.14 is a flowchart showing an example of slave receive mode operation.