Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 658 of 982
REJ09B0054-0600
1
[5]
R/W
[7]
A
23456789 12
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
Data 1
Data 1
Data 1
Slave address
Generate start
condition
Interrupt
request
Interrupt
request
Address + R/W
Address + R/W
[9] IRIC clearance[9] ICDR write[6] IRIC clearance[6] ICDR write[4] Write BBSY = 1
and SCP = 0
(generate start
condition)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
IRIC
IRTR
ICDRT
ICDRS
User processing
Note: Do not write data
to ICDR.
Figure 16.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
[7]
[10]
AA
123456789
Generate start
condition
8 9
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
IRIC
IRTR
ICDR
Bit 7Bit 0 Bit 6
Data 2
Data 2Data 1
Data 1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[12] Write BBSY = 0
and SCP = 0
(generate stop
condition)
[12] IRIC clearance
[11] ACKB read[9] IRIC clearance[9] ICDR write
User processing
Figure 16.9 Example of Master Transmit Mode Stop Condition Generation Timing
(MLS = WAIT = 0)