Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 653 of 982
REJ09B0054-0600
16.3.8 DDC Switch Register (DDCSWR)
DDCSWR controls the I
2
C bus interface format automatic switching function and internal latch
clear.
Bit Bit Name
Initial
Value R/W Description
7 to 4 ⎯ All 0 R/(W)
*
Reserved
The write value should always be 0.
3
2
1
0
CLR3
CLR2
CLR1
CLR0
1
1
1
1
W
W
W
W
I
2
C Bus Interface Clear 3 to 0
When bits CLR3 to CLR0 are set, a clear signal is generated
for the I
2
C bus interface internal latch circuit, and the internal
state is initialized. The write data for these bits is not retained.
To perform I
2
C clearance, bits CLR3 to CLR0 must be written
to simultaneously using an MOV instruction. Do not use a bit
manipulation instruction such as BCLR.
00××: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal Iatch cleared
0111: IIC_0, IIC_1 internal Iatch cleared
1×××: Invalid setting
Legend:
×: Don’t care
Note: * Only 0 can be written to these bits, to clear the flag.
16.4 Operation
The I
2
C bus interface has serial and I
2
C bus formats.
16.4.1 I
2
C Bus Data Format
The I
2
C bus formats are addressing formats and an acknowledge bit is inserted. The first frame
following a start condition always consists of 8 bits. The I
2
C bus format is shown in figure 16.3.
The clocked synchronous serial format is a non-addressing format with no acknowledge bit. This
is shown in figure 16.4. Figure 16.5 shows the I
2
C bus timing.