Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 646 of 982
REJ09B0054-0600
Bit Bit Name
Initial
Value R/W Description
1 IRIC 0 R/W I
2
C Bus Interface Interrupt Request Flag
Also see table 16.4.
[Setting conditions]
In I
2
C bus format master mode
• When a start condition is detected in the bus line state
after a start condition is issued (when the TDRE flag is set
to 1 because of first frame transmission)
• When a wait is inserted between the data and
acknowledge bit when WAIT = 1
• At the end of data transfer (when the TDRE or RDRF flag
is set to 1)
• When a slave address is received after bus arbitration is
lost (when the AL flag is set to1)
• When 1 is received as the acknowledge bit when the
ACKE bit is 1(when the ACKB bit is set to 1)
In I
2
C bus format slave mode
• When the slave address (SVA, SVAX) matches (when the
AAS and AASX flags are set to 1) and at the end of data
transfer up to the subsequent retransmission start
condition or stop condition detection (when the TDRE or
RDRF flag is set to 1)
• When the general call address (one frame including a R/W
bit is H'00) is detected (when the ADZ flag is set to 1) and
at the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection(when the TDRE or RDRF flag is set to 1)
• When 1 is received as the acknowledge bit when the
ACKE bit is 1(when the ACKB bit is set to 1)
• When a stop condition is detected (when the STOP or
ESTP flag is set to 1)
With clocked synchronous serial format
• At the end of data transfer (when the TDRE or RDRF flag
is set to 1)
• When a start condition is detected with serial format
selected
When a condition occurs in which internal flag of TDRE and
RDFR is set to 1 except for the above
[Clearing conditions]
• When 0 is written in IRIC after reading IRIC = 1
• When ICDR is read/written by DTC
(When TDRE or RDRF flag is cleared to 0)
(AS it might not be a condition to clear, for details, see section
16.4.8, Operation Using the DTC).