Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 644 of 982
REJ09B0054-0600
16.3.6 I
2
C Bus Control Register (ICCR)
I
2
C bus control register (ICCR) consists of the control bits and interrupt request flags of I
2
C bus
interface.
Bit Bit Name
Initial
Value R/W Description
7 ICE 0 R/W I
2
C Bus Interface Enable
When this bit is set to 1, the I
2
C bus interface module is
enabled to send/receive data and drive the bus since it is
connected to the SCL and SDA pins. ICMR and ICDR can be
accessed.
SCL and SDA output is disabled (and input to SCL and SDA
is enabled) when this bit is cleared to 0. SAR and SARX can
be accessed.
6 IEIC 0 R/W I
2
C Bus Interface Interrupt Enable
When this bit is 1, interrupts are enabled by IRIC.
5
4
MST
TRS
0
0
R/W Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose in
a bus contention in master mode of the I
2
C bus format. In
slave receive mode, the R/W bit in the first frame immediately
after the start automatically sets these bits in receive mode or
transmit mode by using hardware. The settings can be made
again for the bits that were set/cleared by hardware, by
reading these bits. When the TRS bit is intended to change
during a transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.