Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 640 of 982
REJ09B0054-0600
Table 16.2 Transfer Format
SAR SARX
FS FSX I
2
C Transfer Format
0 0 SAR and SARX are used as the slave addresses with the I
2
C bus
format.
0 1 Only SAR is used as the slave address with the I
2
C bus format.
1 0 Only SARX is used as the slave address with the I
2
C bus format.
1 1 Clock synchronous serial format (SAR and SARX are invalid)
16.3.4 I
2
C Bus Mode Register (ICMR)
ICMR sets the transfer format and transfer rate. It can only be accessed when the ICE bit in ICCR
is 1.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
2
C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I
2
C bus format.
When WAIT is set to 1, after the fall of the clock for the final
data bit, the IRIC flag is set to 1 in ICCR, and a wait state
begins (with SCL at the low level). When the IRIC flag is
cleared to 0 in ICCR, the wait ends and the acknowledge
bit is transferred.
If WAIT is cleared to 0, data and acknowledge bits are
transferred consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the
acknowledge bit transfer, regardless of the WAIT setting.
5
4
3
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Serial Clock Select 2 to 0
This bit is valid only in master mode.
These bits select the required transfer rate, together with
the IICX 1 and IICX0 bit in SCRX. Refer to table 16.3.