Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (12x12) 16-Bit 13 MHz I/O number 72

Section 16 I

2

C Bus Interface (IIC) (Option)

Rev. 6.00 Mar. 18, 2010 Page 635 of 982

REJ09B0054-0600

φ

PS

Noise

canceler

Noise

canceler

Clock

control

Bus state

decision

circuit

Arbitration

decision

circuit

Output data

control

circuit

Address

comparator

SAR, SARX

Interrupt

generator

ICDRS

ICDRR

ICDRT

ICSR

ICMR

ICCR

Internal data bus

Interrupt

request

SCL

SDA

Legend:

ICCR:

ICMR:

ICSR:

ICDR:

SAR:

SARX:

PS:

I

2

C bus control register

I

2

C bus mode register

I

2

C bus status register

I

2

C bus data register

Slave address register

Second slave address register

Prescaler

Figure 16.1 Block Diagram of I

2

C Bus Interface