Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 591 of 982
REJ09B0054-0600
Figure 15.10 shows a sample flowchart for data transmission.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC
*
1
or
the DTC
*
2
is activated by a
transmit-data-empty interrupt (TXI)
request, and data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DR for the port
corresponding to the TxD pin to 0,
clear DDR to 1, then clear the TE
bit in SCR to 0.
Notes: 1. Supported only by the H8S/2239
Group.
2. The case, in which the DTC
automatically checks and clears
the TDRE flag, occurs only when
DISEL in DTC is 0 with the
transfer counter not being 0.
Therefore, the TDRE flag should
be cleared by CPU when DISEL
is 1, or when DISEL is 0 with the
transfer counter being 0.
Figure 15.10 Sample Serial Transmission Flowchart