Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 588 of 982
REJ09B0054-0600
Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Note: Example for H8S/2239 Group with the ABCS bit in SEMR_0 set to a value other than 1.
When ABCS is set to 1, the clock frequency is 8 times the bit rate and sampling of received
data takes place at the fourth rising edge of the basic clock.
Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode
15.4.3 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin when
setting CKE1 = 0 and CKE0 = 1. The frequency of the clock output in this case is equal to the bit
rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as
shown in figure 15.7.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1
11
SCK
TxD
Figure 15.7 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)