Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 569 of 982
REJ09B0054-0600
Bit Bit Name
Initial
Value R/W Description
2 TEND 1 R Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
• When the TE bit in SCR is 0 and the ERS bit is
also 0
• When the ERS bit is 0 and the TDRE bit is 1
after the specified interval following
transmission of 1-byte data. The timing of bit
setting differs according to the register setting
as follows:
When GM = 0 and BLK = 0, 12.5 etu after
transmission starts
When GM = 0 and BLK = 1, 11.5 etu after
transmission starts
When GM = 1 and BLK = 0, 11.0 etu after
transmission starts
When GM = 1 and BLK = 1, 11.0 etu after
transmission starts
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE
= 1
• When the DMAC
*
2
or the DTC
*
3
is activated by
a TXI interrupt and transfers transmission data
to TDR
1 MPB 0 R Multiprocessor Bit
This bit is not used in Smart Card interface mode.
0 MPBT 0 R/W Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Notes: 1. Only 0 can be written to this bit, to clear the flag.
2. Supported only by the H8S/2239 Group.
3. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.