Datasheet
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 537 of 982
REJ09B0054-0600
(c) Setting the IEBus Transmit Message Length Register (IETBFL)
Specify the message length bits.
(d) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET)
Enable the TxRDY (IETxI), TxS, and TxE (IETSI) interrupts.
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
transfer in the vector address (H'000004D4) to be accessed a DTC transfer request is
generated.
2. Set the following data from the start address of the RAM.
⎯ Transfer source address (SAR): Start address of the RAM which stores data to be
transmitted from the data field.
⎯ Transfer destination address (DAR): Address (H'FFF808) of the IEBus transmit buffer
register (IETBR)
⎯ Transfer count (CRA): The same value as IETBFL
3. Set bit DTCEG5 in the DTC enabler register G (DTCERG), and enable the TxRDY interrupt
(IETxI).
Because the TxRDY flag is retained after reset, the DTC transfer is executed when the IETxI is
enabled and the first data field data is written to IETBR. The DTC negates the TxRDY flag
and the DTC transfer of the first byte is completed.
(3) Slave Transmission Flow
Figure 14.12 shows the slave transmission flow. Numbers in the following description correspond
to the numbers in Figure 14.12.
1. After the IEB and DTC have been initialized, a slave communications request command is
issued from IECMR. During slave reception, the command execution status flag (CMX) in
IEFLG is set and the slave communications request will not be issued.
2. The CMX flag is cleared when the slave reception is completed, the slave communications
command is executed, and the SRQ flag is set.
3. If data up to the control field has been received correctly and if the contents of the control bits
is H'3 or H'7, the transmit start detection flag (TxS) in IETSR register is set to 1. In this case,
the TxS flag is cleared in the TxS interrupt handling routine.
4. The slave then transmits the message length field, and the IEB loads the transmit data in the
data field from IETBR when the ACK is received. Then the TxRDY flag is set to 1. A DTC