Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 529 of 982
REJ09B0054-0600
Dn H MA SA CF LFLF D1 D2 Dn-1Dn-1 Dn
IECMR
Slave reception Master transmission
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
CMX
MRQ
SRQ
SRE
TxRDY
TxS
TxF
IETxI (TxRDY)
(TO DTC)
IETxI (TxRDY)
(TO CPU)
IETSI
(TO CPU)
IEFLG
IETSR
Interrupt
(1)
(2)
(2)
(7)
(8)
(8)
(3)
(3)
(4) (5) (6)
(4) (5) (6)
Cleared to 0 byt DTC transfer of 1st byte
Master transmission request
DTC transfer
of 2nd byte
DTC transfer
of 3rd byte
DTC transfer
of nth byte
Figure 14.8 Master Transmit Operation Timing
14.4.2 Slave Receive Operation
This section describes an example of performing a slave reception using the DTC.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Set the
RE bit to 1 to perform reception. The LUEE bit does not need to be specified.
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
(c) Setting the IEBus Receive Interrupt Enable Register (IEIER)
Enable RxRDY (IERxI), RxS, and RxE (IERSI) interrupts.